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Chris R. Jesshope: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chris R. Jesshope
    Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines. [Citation Graph (0, 0)][DBLP]
    ACSAC, 2001, pp:80-88 [Conf]
  2. Chris R. Jesshope
    Multi-threaded Microprocessors - Evolution or Revolution. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:21-45 [Conf]
  3. Chris R. Jesshope
    muTC - An Intermediate Language for Programming Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:147-160 [Conf]
  4. Chris R. Jesshope, Bing Luo
    Micro-Threading: A New Approach to Future RISC. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:34-41 [Conf]
  5. Kostas Bousias, Chris R. Jesshope
    The Challenges of Massive On-Chip Concurrency. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:157-170 [Conf]
  6. Nabil Hasasneh, Ian Bell, Chris R. Jesshope
    Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:252-267 [Conf]
  7. Vladimir Getov, Chris R. Jesshope
    Simulation Facility of Distributed Memory System with "Mad Postman" Communication Network. [Citation Graph (0, 0)][DBLP]
    EDMCC, 1991, pp:224-233 [Conf]
  8. Ramón Beivide, Chris R. Jesshope, Antonio Robles, Cruz Izu
    Topic 12: Routing and Communication in Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:611-612 [Conf]
  9. Chris R. Jesshope
    Parallel Computer Architecture - What Is Its Future? Introduction. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:695-697 [Conf]
  10. Lipeng Wen, Chris R. Jesshope
    A General Learning Management System Based on Schema-driven Methodology. [Citation Graph (0, 0)][DBLP]
    ICALT, 2004, pp:- [Conf]
  11. Lipeng Wen, Chris R. Jesshope
    Web Services Technology and Learning Technology- A Web-Services Model for Constructing Decentralized Virtual Learning Environments. [Citation Graph (0, 0)][DBLP]
    ICWS, 2003, pp:507-514 [Conf]
  12. Regina Gehne, Chris R. Jesshope, Zhenzi Zhang
    Technology Integrated Learning Environment - A Web-based Distance Learning System. [Citation Graph (0, 0)][DBLP]
    IMSA, 2001, pp:1-6 [Conf]
  13. Chris R. Jesshope, P. R. Miller, Jay T. Yantchev
    High Performance Communications in Processor Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:150-157 [Conf]
  14. Chris R. Jesshope, Philip Miller, Jelio Yantchev
    Programming with active data. [Citation Graph (0, 0)][DBLP]
    Parcella, 1988, pp:111-129 [Conf]
  15. Julian A. B. Dines, John F. Snowdon, Marc P. Y. Desmulliez, D. T. Nielson, Dima B. Barsky, Alexander V. Shafarenko, Chris R. Jesshope
    Optical Interconnection hardware for scalable systems. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1996, pp:367-374 [Conf]
  16. Chris R. Jesshope
    Scalable Instruction-Level Parallelism.. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:383-392 [Conf]
  17. Hong Hong, Neena Albi, Kinshuk, Xiaoqin He, Ashok Patel, Chris R. Jesshope
    Adaptivity in Web-based Educational System. [Citation Graph (0, 0)][DBLP]
    WWW Posters, 2001, pp:- [Conf]
  18. Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
    Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Comput. J., 2006, v:49, n:2, pp:211-233 [Journal]
  19. Chris R. Jesshope, Cruz Izu
    The MP1 Network Chip and its Application to Parallel Computers. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1993, v:36, n:8, pp:763-777 [Journal]
  20. Chris R. Jesshope
    Cost-Effective Multimedia in On-line Teaching. [Citation Graph (0, 0)][DBLP]
    Educational Technology & Society, 2001, v:4, n:3, pp:- [Journal]
  21. Chris R. Jesshope
    Computers as Tutors: Solving the Crisis in Education. [Citation Graph (0, 0)][DBLP]
    Educational Technology & Society, 1999, v:2, n:4, pp:- [Journal]
  22. Chris R. Jesshope, Alexander V. Shafarenko
    Guest Editor's Introduction (Part 2). [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2006, v:34, n:4, pp:319-322 [Journal]
  23. Chris R. Jesshope, Alexander V. Shafarenko
    Special issue on Micro-grids - Guest Editor Introduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2006, v:34, n:3, pp:189-192 [Journal]
  24. Ian Bell, Nabil Hasasneh, Chris R. Jesshope
    Supporting Microthread Scheduling and Synchronisation in CMPs. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2006, v:34, n:4, pp:343-381 [Journal]
  25. Julian A. B. Dines, John F. Snowdon, Marc P. Y. Desmulliez, Dima B. Barsky, Alexander V. Shafarenko, Chris R. Jesshope
    Optical Interconnectivity in a Scalable Data-Parallel System. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1997, v:41, n:1, pp:120-130 [Journal]
  26. Chris R. Jesshope
    Transputers and switches as objects in OCCAM. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1988, v:8, n:1-3, pp:19-30 [Journal]
  27. Chris R. Jesshope
    Latency Reduction in VLSI Routers. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1993, v:3, n:, pp:485-494 [Journal]
  28. Chris R. Jesshope
    Microthreading a Model for Distributed Instruction-level Concurrency. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 2006, v:16, n:2, pp:209-228 [Journal]
  29. Chris R. Jesshope, M. J. Crawley, G. L. Lovegrove
    An Intelligent Pascal Editor for a Graphical Oriented Workstation. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1985, v:15, n:11, pp:1103-1119 [Journal]
  30. Chris R. Jesshope
    The Implementation of Fast Radix 2 Transforms on Array Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:1, pp:20-27 [Journal]
  31. Chris R. Jesshope
    Some Results Concerning Data Routing in Array Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:7, pp:659-662 [Journal]
  32. Nabil Hasasneh, Ian Bell, Chris R. Jesshope
    High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids. [Citation Graph (0, 0)][DBLP]
    AICCSA, 2007, pp:301-308 [Conf]
  33. Thuy Duong Vu, Chris R. Jesshope
    Formalizing SANE Virtual Processor in Thread Algebra. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2007, pp:345-365 [Conf]
  34. Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg
    Strategies for Compiling µ TC to Novel Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:127-138 [Conf]
  35. Nabil Hasasneh, Ian Bell, Chris R. Jesshope
    Asynchronous arbiter for micro-threaded chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:5-6, pp:253-262 [Journal]

  36. The Verification of the On-Chip COMA Cache Coherence Protocol. [Citation Graph (, )][DBLP]


  37. Evaluating CMPs and Their Memory Architecture. [Citation Graph (, )][DBLP]


  38. On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores. [Citation Graph (, )][DBLP]


  39. Building a Concurrency and Resource Allocation Model into a Processor's ISA. [Citation Graph (, )][DBLP]


  40. HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? [Citation Graph (, )][DBLP]


  41. Introduction to Programming Multicores. [Citation Graph (, )][DBLP]


  42. A general model of concurrency and its implementation as many-core dynamic RISC processors. [Citation Graph (, )][DBLP]


  43. An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency. [Citation Graph (, )][DBLP]


  44. Web based teaching: a minimalist approach. [Citation Graph (, )][DBLP]


  45. Multi-campus teaching using computer networks. [Citation Graph (, )][DBLP]


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