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Publications of Author

1. Jason Cong, Sung Kyu Lim, Chang Wu
   Performance driven multi-level and multiway partitioning with retiming. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:274-279 [Conf]
   
2. Jason Cong, Honching Li, Chang Wu
   Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:460-465 [Conf]
   
3. Jason Cong, Chang Wu
   FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1997, pp:644-649 [Conf]
   
4. Jason Cong, Chang Wu
   Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. [Citation Graph (0, 0)][DBLP]
   DAC, 1998, pp:330-335 [Conf]
   
5. Jason Cong, Chang Wu, Yuzheng Ding
   Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. [Citation Graph (0, 0)][DBLP]
   FPGA, 1999, pp:29-35 [Conf]
   
6. Jason Cong, Chang Wu
   An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig. [Citation Graph (0, 0)][DBLP]
   ICCD, 1996, pp:572-578 [Conf]
   
7. Jason Cong, Chang Wu
   Global clustering-based performance-driven circuit partitioning. [Citation Graph (0, 0)][DBLP]
   ISPD, 2002, pp:149-154 [Conf]
   
8. Jason Cong, Chang Wu
   An efficient algorithm for performance-optimal FPGA technology mapping with retiming. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:738-748 [Journal]
   
9. Jason Cong, Chang Wu
   Optimal FPGA mapping and retiming with efficient initial state computation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1595-1607 [Journal]
   
10. 
    A NoC Simulation and Verification Platform Based on SystemC. [Citation Graph (, )][DBLP]
    
    
11. 
    Lottery Router: A Customized Arbitral Priority NOC Router. [Citation Graph (, )][DBLP]