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Conferences in DBLP

Design Automation Conference (DAC) (dac)
1997 (conf/dac/97)

  1. Naresh Maheshwari, Sachin S. Sapatnekar
    An Improved Algorithm for Minimum-Area Retiming. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:2-7 [Conf]
  2. Ellen Sentovich, Horia Toma, Gérard Berry
    Efficient Latch Optimization Using Exclusive Sets. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:8-11 [Conf]
  3. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Sequence Compaction for Probabilistic Analysis of Finite-State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:12-15 [Conf]
  4. Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella
    Synthesis of Speed-Independent Circuits from STG-Unfolding Segment. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:16-21 [Conf]
  5. Luca Benini, Enrico Macii, Massimo Poncino
    Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:22-27 [Conf]
  6. Ibrahim M. Elfadel, David D. Ling
    Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:28-33 [Conf]
  7. Kevin J. Kerns, Andrew T. Yang
    Preservation of Passivity During RLC Network Reduction via Split Congruence Transformations. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:34-39 [Conf]
  8. Keith Nabors, Tze-Ting Fang, Hung-Wen Chang, Kenneth S. Kundert
    Lumped Interconnect Models Via Gaussian Quadrature. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:40-45 [Conf]
  9. Florentin Dartu, Lawrence T. Pileggi
    Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:46-51 [Conf]
  10. Felice Balarin, Alberto L. Sangiovanni-Vincentelli
    Schedule Validation for Embedded Reactive Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:52-57 [Conf]
  11. Yosef Gavriel Tirat-Gefen, Diógenes Cecilio da Silva Jr., Alice C. Parker
    Incorporating Imprecise Computation into System-Level Design of Application-Specific Heterogeneous Multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:58-63 [Conf]
  12. Marleen Adé, Rudy Lauwereins, J. A. Peperstraete
    Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:64-69 [Conf]
  13. Stan Y. Liao, Steven W. K. Tjiang, Rajesh K. Gupta
    An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:70-75 [Conf]
  14. Jerry Frenkil
    Tools and Methodologies for Low Power Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:76-81 [Conf]
  15. Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung
    A C-Based RTL Design Verification Methodology for Complex Microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:83-88 [Conf]
  16. Jörg A. Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla, Hans-Jürgen Münster, Kevin W. Kark, Bruce Wile
    Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:89-94 [Conf]
  17. Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh
    Efficient Testing of Clock Regenerator Circuits in Scan Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:95-100 [Conf]
  18. Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen
    A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:101-106 [Conf]
  19. Yibin Ye, Kaushik Roy
    A Graph-Based Synthesis Algorithm for AND/XOR Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:107-112 [Conf]
  20. Tai-Hung Liu, Khurram Sajid, Adnan Aziz, Vigyan Singhal
    Optimizing Designs Containing Black Boxes. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:113-116 [Conf]
  21. Stan Y. Liao, Srinivas Devadas
    Solving Covering Problems Using LPR-Based Lower Bounds. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:117-120 [Conf]
  22. Olivier Coudert
    Exact Coloring of Real-Life Graphs is Easy. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:121-126 [Conf]
  23. E. Aykut Dengi, Ronald A. Rohrer
    Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI Interconnect Modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:127-132 [Conf]
  24. Michael W. Beattie, Lawrence T. Pileggi
    Bounds for BEM Capacitance Extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:133-136 [Conf]
  25. Zhijiang He, Mustafa Celik, Lawrence T. Pileggi
    SPIE: Sparse Partial Inductance Extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:137-140 [Conf]
  26. Sharad Kapur, Jinsong Zhao
    A Fast Method of Moments Solver for Efficient Parameter Extraction of MCMs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:141-146 [Conf]
  27. Sharad Malik, Margaret Martonosi, Yau-Tsun Steven Li
    Static Timing Analysis of Embedded Software. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:147-152 [Conf]
  28. Yanbing Li, Wayne Wolf
    A Task-Level Hierarchical Memory Model for System Synthesis of Multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:153-156 [Conf]
  29. Rajeshkumar S. Sambandam, Xiaobo Hu
    Predicting Timing Behavior in Architectural Design Exploration of Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:157-160 [Conf]
  30. Kyle L. Nelson, Alok Jain, Randal E. Bryant
    Formal Verification of a Superscalar Execution Unit. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:161-166 [Conf]
  31. Manish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir
    Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:167-172 [Conf]
  32. Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl Pixley
    Formal Verification of FIRE: A Case Study. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:173-177 [Conf]
  33. James A. Rowson, Alberto L. Sangiovanni-Vincentelli
    Interface-Based Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:178-183 [Conf]
  34. Robert H. Klenke, Moshe Meyassed, James H. Aylor, Barry W. Johnson, Ramesh Rao, Anup Ghosh
    An Integrated Design Environment for Performance and Dependability Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:184-189 [Conf]
  35. Ole Bentz, Jan M. Rabaey, David Lidsky
    A Dynamic Design Estimation and Exploration Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:190-195 [Conf]
  36. Srilatha Manne, Dirk Grunwald, Fabio Somenzi
    Remembrance of Things Past: Locality and Memory in BDDs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:196-201 [Conf]
  37. Christoph Meinel, Fabio Somenzi, Thorsten Theobald
    Linear Sifting of Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:202-207 [Conf]
  38. Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan
    Safe BDD Minimization Using Don't Cares. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:208-213 [Conf]
  39. John Lillis, Chung-Kuan Cheng
    Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:214-219 [Conf]
  40. Yuji Kukimoto, Robert K. Brayton
    Exact Required Time Analysis via False Path Detection. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:220-225 [Conf]
  41. Tod Amon, Gaetano Borriello, Taokuan Hu, Jiwen Liu
    Symbolic Timing Verification of Timing Diagrams using Presburger Formulas. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:226-231 [Conf]
  42. Peter Marwedel
    Code Generation for Core Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:232-237 [Conf]
  43. Ajay J. Daga, Peter Suaris
    Interface Timing Verification Drives System Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:240-245 [Conf]
  44. Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura
    Memory-CPU Size Optimization for Embedded System Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:246-251 [Conf]
  45. Miodrag Potkonjak, Kyosun Kim, Ramesh Karri
    Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:252-257 [Conf]
  46. Robert P. Kurshan
    Formal Verification in a Commercial Setting. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:258-262 [Conf]
  47. Andreas Kuehlmann, Florian Krohm
    Equivalence Checking Using Cuts and Heaps. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:263-268 [Conf]
  48. Jaijeet S. Roychowdhury
    Efficient Methods for Simulating Highly Nonlinear Multi-Rate Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:269-274 [Conf]
  49. Michael W. Tian, C.-J. Richard Shi
    Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:275-280 [Conf]
  50. Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas
    SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:281-286 [Conf]
  51. Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
    Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:287-292 [Conf]
  52. Markus Willems, Volker Bürsgens, Holger Keding, Thorsten Grötker, Heinrich Meyr
    System Level Fixed-Point Design Based on an Interpolative Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:293-298 [Conf]
  53. George Hadjiyiannis, Silvina Hanono, Srinivas Devadas
    ISDL: An Instruction Set Description Language for Retargetability. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:299-302 [Conf]
  54. Mark R. Hartoog, James A. Rowson, Prakash D. Reddy, Soumya Desai, Douglas D. Dunlop, Edwin A. Harcourt, Neeti Khullar
    Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:303-306 [Conf]
  55. Hugo De Man
    Education for the Deep Submicron Age: Business as Usual? [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:307-312 [Conf]
  56. Robert W. Brodersen
    InfoPad - An Experiment in System Level Design and Integration. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:313-314 [Conf]
  57. Asim Smailagic, Daniel P. Siewiorek, Richard Martin, John Stivoric
    Very Rapid Prototyping of Wearable Computers: A Case Study of Custom versus Off-the-Shelf Design Methodologies. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:315-320 [Conf]
  58. Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz
    CAD at the Design-Manufacturing Interface. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:321-326 [Conf]
  59. Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernandez, Larry G. Jones
    CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:327-332 [Conf]
  60. Donald G. Baltus, Thomas Varga, Robert C. Armstrong, John Duh, T. G. Matheson
    Developing a Concurrent Methodology for Standard-Cell Library Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:333-336 [Conf]
  61. John F. Croix, D. F. Wong
    A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:337-340 [Conf]
  62. Jian Li, Rajesh K. Gupta
    Limited Exception Modeling and Its Use in Presynthesis Optimizations. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:341-346 [Conf]
  63. Inki Hong, Darko Kirovski, Miodrag Potkonjak
    Potential-Driven Statistical Ordering of Transformations. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:347-352 [Conf]
  64. Kyosun Kim, Ramesh Karri, Miodrag Potkonjak
    Synthesis of Application Specific Programmable Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:353-358 [Conf]
  65. Jeffrey Walrath, Ranga Vemuri
    Symbolic Evaluation of Performance Models for Tradeoff Visualization. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:359-364 [Conf]
  66. Subodh Gupta, Farid N. Najm
    Power Macromodeling for High Level Power Estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:365-370 [Conf]
  67. Chih-Shun Ding, Qing Wu, Cheng-Ta Hsieh, Massoud Pedram
    Statistical Estimation of the Cumulative Distribution Function for Power Dissipation in VLSI Cirucits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:371-376 [Conf]
  68. Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang
    Statistical Estimation of Average Power Dissipation in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:377-382 [Conf]
  69. Angela Krstic, Kwang-Ting Cheng
    Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:383-388 [Conf]
  70. Claudio Passerone, Luciano Lavagno, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli
    Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:389-394 [Conf]
  71. Ken Hines, Gaetano Borriello
    Dynamic Communication Models in Embedded System Co-Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:395-400 [Conf]
  72. Pankaj Pant, Vivek De, Abhijit Chatterjee
    Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:403-408 [Conf]
  73. James Kao, Anantha Chandrakasan, Dimitri Antoniadis
    Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:409-414 [Conf]
  74. Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha Chandrakasan
    Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:415-420 [Conf]
  75. Chi-Ying Tsui, Kai-Keung Chan, Qing Wu, Chih-Shun Ding, Massoud Pedram
    A Power Estimation Framework for Designing Low Power Portable Video Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:421-424 [Conf]
  76. Qi Wang, Sarma B. K. Vrudhula, Shantanu Ganguly
    An Investigation of Power Delay Trade-Offs on PowerPC Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:425-428 [Conf]
  77. Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
    Power Management Techniques for Control-Flow Intensive Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:429-434 [Conf]
  78. Catherine H. Gebotys
    Low Energy Memory and Register Allocation Using Network Flow. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:435-440 [Conf]
  79. Daehong Kim, Kiyoung Choi
    Power-conscious High Level Synthesis Using Loop Folding. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:441-445 [Conf]
  80. Martin Lefebvre, David Marple, Carl Sechen
    The Future of Custom Cell Generation in Physical Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:446-451 [Conf]
  81. Avaneendra Gupta, John P. Hayes
    CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:452-455 [Conf]
  82. Jaewon Kim, Sung-Mo Kang
    An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:456-459 [Conf]
  83. John Lakos
    Technology Retargeting for IC Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:460-465 [Conf]
  84. Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng
    A Test Synthesis Approach to Reducing BALLAST DFT Overhead. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:466-471 [Conf]
  85. Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska
    STARBIST: Scan Autocorrelated Random Pattern Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:472-477 [Conf]
  86. Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik
    A Hybrid Algorithm for Test Point Selection for Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:478-483 [Conf]
  87. Wolfgang Meyer, Andrew Seawright, Fumiya Tada
    Design and Synthesis of Array Structured Telecommunication Processing Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:486-491 [Conf]
  88. C. Hein, J. Pridgen, W. Kline
    RASSP Virtual Prototyping of DSP Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:492-497 [Conf]
  89. Claus Schneider
    A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:498-503 [Conf]
  90. Enrico Macii, Massoud Pedram, Fabio Somenzi
    High-Level Power Modeling, Estimation, and Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:504-511 [Conf]
  91. Ming-Ter Kuo, Chung-Kuan Cheng
    A Network Flow Approach for Hierarchical Tree Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:512-517 [Conf]
  92. Wen-Jong Fang, Allen C.-H. Wu
    Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:518-521 [Conf]
  93. Helena Krupnova, Ali Abbara, Gabriele Saucier
    A Hierarchy-Driven FPGA Partitioning Method. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:522-525 [Conf]
  94. George Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar
    Multilevel Hypergraph Partitioning: Application in VLSI Domain. [Citation Graph (1, 0)][DBLP]
    DAC, 1997, pp:526-529 [Conf]
  95. Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng
    Multilevel Circuit Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:530-533 [Conf]
  96. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha
    Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:534-539 [Conf]
  97. Laurence Goodby, Alex Orailoglu
    Frequency-Domain Compatibility in Digital Filter BIST. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:540-545 [Conf]
  98. Mehrdad Nourani, Joan Carletta, Christos A. Papachristou
    A Scheme for Integrated Controller-Datapath Fault Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:546-551 [Conf]
  99. Hemang Lavana, Amit Khetawat, Franc Brglez, Krzysztof Kozminski
    Executable Workflows: A Paradigm for Collaborative Design on the Internet. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:553-558 [Conf]
  100. Donald R. Cottrell
    Electronic Component Information Exchange (ECIX). [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:559-563 [Conf]
  101. Bernd Schürmann, Joachim Altmeyer
    Modeling Design Tasks and Tools: The Link Between Product and Flow Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:564-569 [Conf]
  102. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Hierarchical Sequence Compaction for Power Estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:570-575 [Conf]
  103. Cheng-Ta Hsieh, Massoud Pedram, Gaurav Mehta, Fred Rastgar
    Profile-Driven Program Synthesis for Evaluation of System Power Dissipation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:576-581 [Conf]
  104. Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
    Analytical Estimation of Transition Activity From Word-Level Signal Statistics. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:582-587 [Conf]
  105. Charles J. Alpert, Anirudh Devgan
    Wire Segmenting for Improved Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:588-593 [Conf]
  106. Andrew B. Kahng, Chung-Wen Albert Tsao
    More Practical Bounded-Skew Clock Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:594-599 [Conf]
  107. Chin-Chih Chang, Jason Cong
    An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:600-603 [Conf]
  108. Chung-Ping Chen, D. F. Wong
    Optimal Wire-Sizing Function with Fringing Capacitance Consideration. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:604-607 [Conf]
  109. Irith Pomeranz, Sudhakar M. Reddy
    Fault Simulation under the Multiple Observation Time Approach using Backward Implications. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:608-613 [Conf]
  110. Seongmoon Wang, Sandeep K. Gupta
    ATPG for Heat Dissipation Minimization During Scan Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:614-619 [Conf]
  111. Oriol Roig, Jordi Cortadella, Marco A. Peña, Enric Pastor
    Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:620-625 [Conf]
  112. Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen
    Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:627-632 [Conf]
  113. Cristiano Forzan, Bruno Franzini, Carlo Guardiani
    Accurate and Efficient Macromodel of Submicron Digital Standard Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:633-637 [Conf]
  114. Howard H. Chen, David D. Ling
    Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:638-643 [Conf]
  115. Jason Cong, Chang Wu
    FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:644-649 [Conf]
  116. Rajendran Panda, Farid N. Najm
    Technology-Dependent Transformations for Low-Power Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:650-655 [Conf]
  117. Chau-Shen Chen, TingTing Hwang, C. L. Liu
    Low Power FPGA Design - A Re-engineering Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:656-661 [Conf]
  118. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska
    Post-Layout Logic Restructuring for Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:662-665 [Conf]
  119. Masako Murofushi, Takashi Ishioka, Masami Murakata, Takashi Mitsuhashi
    Layout Driven Re-synthesis for Low Power Consumption LSIs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:666-669 [Conf]
  120. William C. Tang
    Overview of Microelectromechanical Systems and Design Processes. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:670-673 [Conf]
  121. Jean-Michel Karam, Bernard Courtois, Hicham Boutamine, P. Drake, A. Poppe, Vladimir Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner
    CAD and Foundries for Microsystems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:674-679 [Conf]
  122. Tamal Mukherjee, Gary K. Fedder
    Structured Design of Microelectromechanical Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:680-685 [Conf]
  123. Narayan R. Aluru, James White
    Algorithms for Coupled Domain MEMS Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:686-690 [Conf]
  124. Jörg Henkel, Rolf Ernst
    A Hardware/Software Partitioner Using a Dynamically Determined Granularity. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:691-696 [Conf]
  125. Darko Kirovski, Miodrag Potkonjak
    System-Level Synthesis of Low-Power Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:697-702 [Conf]
  126. Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha
    COSYN: Hardware-Software Co-Synthesis of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:703-708 [Conf]
  127. Samir Agrawal, Rajesh K. Gupta
    Data-Flow Assisted Behavioral Partitioning for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:709-712 [Conf]
  128. Smita Bakshi, Daniel Gajski
    Hardware/Software Partitioning and Pipelining. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:713-716 [Conf]
  129. Wayne Wei-Ming Dai
    Chip Parasitic Extraction and Signal Integrity Verification (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:717-719 [Conf]
  130. William J. Grundmann, Dan Dobberpuhl, Randy L. Allmon, Nicholas L. Rethman
    Designing High Performance CMOS Microprocessors Using Full Custom Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:722-727 [Conf]
  131. Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer
    Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:728-733 [Conf]
  132. Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
    An Efficient Assertion Checker for Combinational Properties. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:734-739 [Conf]
  133. Aarti Gupta, Sharad Malik, Pranav Ashar
    Toward Formalizing a Validation Methodology Using Simulation Coverage. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:740-745 [Conf]
  134. Jens Vygen
    Algorithms for Large-Scale Flat Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:746-751 [Conf]
  135. Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan
    Quadratic Placement Revisited. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:752-757 [Conf]
  136. Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez
    Unification of Budgeting and Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:758-761 [Conf]
  137. Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
    Cluster Refinement for Block Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:762-765 [Conf]
  138. Steven P. Levitan, Philippe J. Marchand, Timothy P. Kurzweg, M. A. Rempel, Donald M. Chiarulli, C. Fan, F. B. McCormick
    Computer-Aided Design of Free-Space Opto-Electronic Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:768-773 [Conf]
  139. Matthias Bauer, Wolfgang Ecker
    Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:774-779 [Conf]
  140. Clifford Liem, Marco Cornero, Miguel Santana, Pierre G. Paulin, Ahmed Amine Jerraya, Jean-Marc Gentit, Jean Lopez, Xavier Figari, Laurent Bergher
    Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:780-785 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
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