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Jin-fuw Lee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jin-fuw Lee, Donald T. Tang
    An Algorithm for Incremental Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:696-701 [Conf]
  2. Jin-fuw Lee, Daniel L. Ostapko, Jeffery Soreff, C. K. Wong
    On the Signal Bounding Problem in Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:507-514 [Conf]
  3. Jin-fuw Lee, Donald T. Tang
    HIMALAYAS - a hierarchical compaction system with a minimized constraint set. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:150-157 [Conf]
  4. Jin-fuw Lee, Donald T. Tang, C. K. Wong
    A timing analysis algorithm for circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:743-748 [Conf]
  5. Jin-fuw Lee
    A Layout Compaction Algorithm with Multiple Grid Constraints. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:30-33 [Conf]
  6. Jin-fuw Lee
    A new framework of design rules for compaction of VLSI layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1195-1204 [Journal]
  7. Jin-fuw Lee, Donald T. Tang
    VLSI Layout Compaction with Grid and Mixed Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:903-910 [Journal]
  8. Jin-fuw Lee, Donald T. Tang, Chak-Kuen Wong
    A timing analysis algorithm for circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:535-543 [Journal]
  9. Jin-fuw Lee, Chak-Kuen Wong
    A performance-aimed cell compactor with automatic jogs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1495-1507 [Journal]

  10. Yield estimation of SRAM circuits using "Virtual SRAM Fab". [Citation Graph (, )][DBLP]


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