Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1987, volume: 6, number: 5

1. Chin Jen Lin, Sudhakar M. Reddy
   On Delay Fault Testing in Logic Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:694-703 [Journal]
   
2. Kurt Antreich, Michael H. Schulz
   Accelerated Fault Simulation and Fault Grading in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:704-712 [Journal]
   
3. Abhijit Chatterjee, Jacob A. Abraham
   On the C-Testability of Generalized Counters. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:713-726 [Journal]
   
4. Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli
   Multiple-Valued Minimization for PLA Optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:727-750 [Journal]
   
5. Giovanni De Micheli
   Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:751-765 [Journal]
   
6. Douglas S. Reeves, Mary Jane Irwin
   Fast Methods for Switch-Level Verification of MOS Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:766-779 [Journal]
   
7. Erik C. Carlson, Rob A. Rutenbar
   A Scanline Data Structure Processor for VLSI Geometry Checking. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:780-794 [Journal]
   
8. Shmuel Wimer, Ron Y. Pinter, Jack A. Feldman
   Optimal Chaining of CMOS Transistors in a Functional Cell. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:795-801 [Journal]
   
9. D. K. Hwang, W. Kent Fuchs, Sung-Mo Kang
   An Efficient Approach to Gate Matrix Layout. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:802-809 [Journal]
   
10. K. Winter, Dieter A. Mlynski
    Hierarchical Loose Routing for Gate Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:810-819 [Journal]
    
11. Gregory B. Sorkin
    Asymptotically Perfect Trivial Global Routing: A Stochastic Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:820-827 [Journal]
    
12. Wayne Wei-Ming Dai, Ernest S. Kuh
    Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:828-837 [Journal]
    
13. Andrea Casotto, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli
    A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:838-847 [Journal]
    
14. William A. Rogers, John F. Guzolek, Jacob A. Abraham
    Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:848-862 [Journal]
    
15. Jürgen Doenhardt, Thomas Lengauer
    Algorithmic Aspects of One-Dimensional Layout Compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:863-878 [Journal]
    
16. Antonio Gnudi, Paolo Ciampolini, Roberto Guerrieri, Massimo Rudan, Giorgio Baccarani
    Sensitivity Analysis for Device Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:879-885 [Journal]
    
17. Sung-Mo Kang
    Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:886-891 [Journal]
    
18. Donald L. Dietmeyer
    Local Transformations via Cube Operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:892-902 [Journal]
    
19. Jin-fuw Lee, Donald T. Tang
    VLSI Layout Compaction with Grid and Mixed Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:903-910 [Journal]