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Ernest S. Kuh :
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Zhengyong Zhu , Khosro Rouz , Manjit Borah , Chung-Kuan Cheng , Ernest S. Kuh Efficient transient simulation for transistor-level analysis. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:240-243 [Conf ] Zhengyong Zhu , Rui Shi , Chung-Kuan Cheng , Ernest S. Kuh An unconditional stable general operator splitting method for transistor level transient analysis. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2006, pp:428-433 [Conf ] Pinghong Chen , Ernest S. Kuh Floorplan sizing by linear programming approximation. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:468-471 [Conf ] Wayne Wei-Ming Dai , Masao Sato , Ernest S. Kuh A Dynamic and Efficient Representation of Building-Block Layout. [Citation Graph (0, 0)][DBLP ] DAC, 1987, pp:376-384 [Conf ] Xianlong Hong , Jin Huang , Chung-Kuan Cheng , Ernest S. Kuh FARM: An Efficient Feed-Through Pin Assignment Algorithm. [Citation Graph (0, 0)][DBLP ] DAC, 1992, pp:530-535 [Conf ] Xianlong Hong , Tianxiong Xue , Ernest S. Kuh , Chung-Kuan Cheng , Jin Huang Performance-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:177-181 [Conf ] Jin Huang , Xianlong Hong , Chung-Kuan Cheng , Ernest S. Kuh An Efficient Timing-Driven Global Routing Algorithm. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:596-600 [Conf ] Michael A. B. Jackson , Ernest S. Kuh Performance-driven Placement of Cell Based IC's. [Citation Graph (0, 0)][DBLP ] DAC, 1989, pp:370-375 [Conf ] Michael A. B. Jackson , Arvind Srinivasan , Ernest S. Kuh Clock Routing for High-Performance ICs. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:573-579 [Conf ] Shen Lin , Ernest S. Kuh Transient Simulation of Lossy Interconnect. [Citation Graph (0, 0)][DBLP ] DAC, 1992, pp:81-86 [Conf ] Shen Lin , Malgorzata Marek-Sadowska , Ernest S. Kuh Delay and Area Optimization in Standard-Cell Design. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:349-352 [Conf ] Takashi Mitsuhashi , Ernest S. Kuh Power and Ground Network Topology Optimization for Cell Based VLSIs. [Citation Graph (0, 0)][DBLP ] DAC, 1992, pp:524-529 [Conf ] Minshine Shih , Ernest S. Kuh Quadratic Boolean Programming for Performance-Driven System Partitioning. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:761-765 [Conf ] Minshine Shih , Ernest S. Kuh , Ren-Song Tsay Performance-Driven System Partitioning on Multi-Chip Modules. [Citation Graph (0, 0)][DBLP ] DAC, 1992, pp:53-56 [Conf ] Ren-Song Tsay , Ernest S. Kuh , Chi-Ping Hsu Proud: A Fast Sea-of-Gates Placement Algorithm. [Citation Graph (0, 0)][DBLP ] DAC, 1988, pp:318-323 [Conf ] Xiao-Ming Xiong , Ernest S. Kuh Nutcracker: An Efficient and Intelligent Channel Spacer. [Citation Graph (0, 0)][DBLP ] DAC, 1987, pp:298-304 [Conf ] Xiao-Ming Xiong , Ernest S. Kuh The Constrained Via Minimization Problem for PCB and VLSI Design. [Citation Graph (0, 0)][DBLP ] DAC, 1988, pp:573-578 [Conf ] Qingjian Yu , Janet Meiling Wang , Ernest S. Kuh Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:520-525 [Conf ] Qingjian Yu , Ernest S. Kuh Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements. [Citation Graph (0, 0)][DBLP ] DATE, 2001, pp:445-450 [Conf ] Dongsheng Wang , Ernest S. Kuh A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:466-470 [Conf ] Janet Meiling Wang , Qingjian Yu , Ernest S. Kuh Coupled Noise Estimation for Distributed RC Interconnect Model. [Citation Graph (0, 0)][DBLP ] DATE, 1999, pp:664-668 [Conf ] Dongsheng Wang , Ernest S. Kuh Performance-Driven Interconnect Global Routing. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1996, pp:132-136 [Conf ] Shuji Tsukiyama , Ernest S. Kuh , Isao Shirakawa On the layering problem of multilayer PWB wiring. [Citation Graph (0, 0)][DBLP ] Graph Theory and Algorithms, 1980, pp:20-37 [Conf ] Kamal Chaudhary , Akira Onozawa , Ernest S. Kuh A spacing algorithm for performance enhancement and cross-talk reduction. [Citation Graph (0, 0)][DBLP ] ICCAD, 1993, pp:697-702 [Conf ] Michael A. B. Jackson , Arvind Srinivasan , Ernest S. Kuh A Fast Algorithm for Performance-Driven Placement. [Citation Graph (0, 0)][DBLP ] ICCAD, 1990, pp:328-331 [Conf ] Jun-Fa Mao , Janet Meiling Wang , Ernest S. Kuh Simulation and sensitivity analysis of transmission line circuits by the characteristics method. [Citation Graph (0, 0)][DBLP ] ICCAD, 1996, pp:556-562 [Conf ] Massoud Pedram , Malgorzata Marek-Sadowska , Ernest S. Kuh Floorplanning with Pin Assignment. [Citation Graph (0, 0)][DBLP ] ICCAD, 1990, pp:98-101 [Conf ] Arvind Srinivasan , Kamal Chaudhary , Ernest S. Kuh RITUAL: Performance Driven Placement Algorithm for Small Cell ICs. [Citation Graph (0, 0)][DBLP ] ICCAD, 1991, pp:48-51 [Conf ] Tianxiong Xue , Ernest S. Kuh , Dongsheng Wang Post global routing crosstalk risk estimation and reduction. [Citation Graph (0, 0)][DBLP ] ICCAD, 1996, pp:302-309 [Conf ] Janet Meiling Wang , Ernest S. Kuh , Qingjian Yu The Chebyshev expansion based passive model for distributed interconnect networks. [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:370-375 [Conf ] Qingjian Yu , Janet Meiling Wang , Ernest S. Kuh Multipoint moment matching model for multiport distributed interconnect networks. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:85-91 [Conf ] Tianxiong Xue , Ernest S. Kuh Post routing performance optimization via multi-link insertion and non-uniform wiresizing. [Citation Graph (0, 0)][DBLP ] ICCAD, 1995, pp:575-580 [Conf ] Massoud Pedram , Kamal Chaudhary , Ernest S. Kuh I/O Pad Assignment Based on the Circuit Structure. [Citation Graph (0, 0)][DBLP ] ICCD, 1991, pp:314-318 [Conf ] Premal Buch , Shen Lin , Vijay Nagasamy , Ernest S. Kuh Techniques for fast circuit simulation applied to power estimation of CMOS circuits. [Citation Graph (0, 0)][DBLP ] ISLPD, 1995, pp:135-138 [Conf ] Ernest S. Kuh Physical design: reminiscing and looking ahead. [Citation Graph (0, 0)][DBLP ] ISPD, 1997, pp:206- [Conf ] Hiroshi Murata , Ernest S. Kuh Sequence-pair based placement method for hard/soft/pre-placed modules. [Citation Graph (0, 0)][DBLP ] ISPD, 1998, pp:167-172 [Conf ] Qingjian Yu , Ernest S. Kuh New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees. [Citation Graph (0, 0)][DBLP ] ISQED, 2001, pp:151-157 [Conf ] Shen Lin , Ernest S. Kuh Circuit simulation for large interconnected IC networks. [Citation Graph (0, 0)][DBLP ] VLSI, 1993, pp:333-342 [Conf ] Tianxiong Xue , Takashi Fujii , Ernest S. Kuh A new performance-driven global routing algorithm for gate array. [Citation Graph (0, 0)][DBLP ] VLSI, 1993, pp:321-330 [Conf ] Premal Buch , Ernest S. Kuh SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1997, pp:403-407 [Conf ] Kwang-Ting Cheng , Vishwani D. Agrawal , Ernest S. Kuh A Simulation-Based Method for Generating Tests for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1990, v:39, n:12, pp:1456-1463 [Journal ] Howard H. Chen , Ernest S. Kuh Glitter: A Gridless Variable-Width Channel Router. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:459-465 [Journal ] Chung-Kuan Cheng , Ernest S. Kuh Module Placement Based on Resistive Network Optimization. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:218-225 [Journal ] Wayne Wei-Ming Dai , Tetsuo Asano , Ernest S. Kuh Routing Region Definition and Ordering Scheme for Building-Block Layout. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:189-197 [Journal ] Wayne Wei-Ming Dai , Ernest S. Kuh Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:828-837 [Journal ] Xianlong Hong , Tianxiong Xue , Jin Huang , Chung-Kuan Cheng , Ernest S. Kuh TIGER: an efficient timing-driven global router for gate array and standard cell layout design. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1323-1331 [Journal ] Ernest S. Kuh Editorial: Routing in Microelectronics. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:4, pp:213-214 [Journal ] Shen Lin , Ernest S. Kuh , Malgorzata Marek-Sadowska Stepwise equivalent conductance circuit simulation technique. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:672-683 [Journal ] Akira Onozawa , Kamal Chaudhary , Ernest S. Kuh Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:707-719 [Journal ] Tom Tsan-Kuo Tarng , Malgorzata Marek-Sadowska , Ernest S. Kuh An Efficient Single-Row Routing Algorithm. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:178-183 [Journal ] Shuji Tsukiyama , Ernest S. Kuh , Isao Shirakawa On the Layering Problem of Multilayer PWB Wiring. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:1, pp:30-38 [Journal ] Tianxiong Xue , Ernest S. Kuh , Dongsheng Wang Post global routing crosstalk synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:12, pp:1418-1430 [Journal ] Takeshi Yoshimura , Ernest S. Kuh Efficient Algorithms for Channel Routing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1982, v:1, n:1, pp:25-35 [Journal ] Henrik Esbensen , Ernest S. Kuh A performance-driven IC/MCM placement algorithm featuring explicit design space exploration. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:1, pp:62-80 [Journal ] Qingjian Yu , Ernest S. Kuh Exact moment matching model of transmission lines and application to interconnect delay estimation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:311-322 [Journal ] Qingjian Yu , Ernest S. Kuh , Tianxiong Xue Moment models of general transmission lines with application to interconnect analysis and optimization. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:477-494 [Journal ] High performance on-chip differential signaling using passive compensation for global communication. [Citation Graph (, )][DBLP ] Low power passive equalizer optimization using tritonic step response. [Citation Graph (, )][DBLP ] Post routing performance optimization via tapered link insertion and wiresizing. [Citation Graph (, )][DBLP ] MOLE: a sea-of-gates detailed router. [Citation Graph (, )][DBLP ] Low Power Passive Equalizer Design for Computer Memory Links. [Citation Graph (, )][DBLP ] Efficient and accurate eye diagram prediction for high speed signaling. [Citation Graph (, )][DBLP ] Design methodology of high performance on-chip global interconnect using terminated transmission-line. [Citation Graph (, )][DBLP ] Search in 0.074secs, Finished in 0.078secs