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Krishnan Sundaresan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Krishnan Sundaresan, Nihar R. Mahapatra
    Value-based bit ordering for energy optimization of on-chip global signal buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:624-625 [Conf]
  2. Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra
    Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:111-114 [Conf]
  3. Krishnan Sundaresan, Nihar R. Mahapatra
    Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:51-60 [Conf]
  4. Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra
    Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:458-463 [Conf]
  5. Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan
    Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:234-239 [Conf]
  6. Jiangjiang Liu, Nihar R. Mahapatra, Krishnan Sundaresan
    Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:220-221 [Conf]
  7. Krishnan Sundaresan, Nihar R. Mahapatra
    Code Compression Techniques for Embedded Systems and Their Effectiveness. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:262-263 [Conf]
  8. Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan
    The performance advantage of applying compression to the memory system. [Citation Graph (0, 0)][DBLP]
    MSP/ISMM, 2002, pp:86-96 [Conf]
  9. Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra
    Energy-Efficient Compressed Address Transmission. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:592-597 [Conf]
  10. Krishnan Sundaresan, Nihar R. Mahapatra
    An Accurate Energy and Thermal Model for Global Signal Buses. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:685-690 [Conf]
  11. Krishnan Sundaresan, Nihar R. Mahapatra
    An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:515-520 [Conf]

  12. Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses. [Citation Graph (, )][DBLP]


  13. Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. [Citation Graph (, )][DBLP]


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