Conferences in DBLP
Fred Weber Trends in High-Performance Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Nathan Tuck , Dean M. Tullsen Multithreaded Value Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Nevin Kirman , Meyrem Kirman , Mainak Chaudhuri , José F. Martínez Checkpointed Early Load Retirement. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Balasubramonian , Naveen Muralimanohar , Karthik Ramani , Venkatanand Venkatachalapathy Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Masaaki Kondo , Hiroshi Nakamura A Small, Fast and Low-Power Register File by Bit-Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Sundaresan , Nihar R. Mahapatra Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Chaparro , Grigorios Magklis , José González , Antonio González Distributing the Frontend for Temperature Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Yingmin Li , David Brooks , Zhigang Hu , Kevin Skadron Performance, Energy, and Thermal Considerations for SMT and CMP Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi K. Venkatesan , Ahmed S. Al-Zawawi , Eric Rotenberg Tapping ZettaRAMTM for Low-Power Memory Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Willmann , Hyong-youb Kim , Scott Rixner , Vijay S. Pai An Efficient Programmable 10 Gigabit Ethernet Network Interface Card. [Citation Graph (0, 0)][DBLP ] Conf ] José Duato , Ian Johnson , Jose Flich , Finbar Naven , Pedro Javier García , Teresa Nachiondo Frinós A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Xuning Chen , Li-Shiuan Peh , Gu-Yeon Wei , Yue-Kai Huang , Paul R. Prucnal Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jung Ho Ahn , Mattan Erez , William J. Dally Scatter-Add in Data Parallel Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy M. Jones , Michael F. P. O'Boyle , Jaume Abella , Antonio González Software Directed Issue Queue Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Yan Meng , Timothy Sherwood , Ryan Kastner On the Limits of Leakage Power Reduction in Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Jahangir Hasan , Ankit Jalote , T. N. Vijaykumar , Carla E. Brodley Heat Stroke: Power-Density-Based Denial of Service in SMT. [Citation Graph (0, 0)][DBLP ] Conf ] Qiang Wu , Philo Juang , Margaret Martonosi , Douglas W. Clark Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Aamer Jaleel , Bruce L. Jacob Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Erik G. Hallnor , Steven K. Reinhardt A Unified Compressed Memory Hierarchy. [Citation Graph (0, 0)][DBLP ] Conf ] Zhichun Zhu , Zhao Zhang A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence Spracklen , Yuan Chou , Santosh G. Abraham Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Hans M. Jacobson , Pradip Bose , Zhigang Hu , Alper Buyuktosunoglu , Victor V. Zyuban , Rick Eickemeyer , Lee Eisen , John Griswell , Doug Logan , Balaram Sinharoy , Joel M. Tendler Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt The Soft Error Problem: An Architectural Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence Spracklen , Santosh G. Abraham Chip Multithreading: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Parthasarathy Ranganathan , Norman P. Jouppi Enterprise IT Trends and Implications for Architecture Research. [Citation Graph (0, 0)][DBLP ] Conf ] H. Peter Hofstee Power Efficient Processor Architecture and The Cell Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-mei W. Hwu , Sanjay J. Patel The Future of Computer Architecture Research: An Industrial Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Joshua J. Yi , Sreekumar V. Kodakara , Resit Sendag , David J. Lilja , Douglas M. Hawkins Characterizing and Comparing Prevailing Simulation Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy Lau , Stefan Schoenmackers , Brad Calder Transition Phase Classification and Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Qin , Shan Lu , Yuanyuan Zhou SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs. [Citation Graph (0, 0)][DBLP ] Conf ] Marc L. Corliss , E. Christopher Lewis , Amir Roth Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE. [Citation Graph (0, 0)][DBLP ] Conf ] C. Scott Ananian , Krste Asanovic , Bradley C. Kuszmaul , Charles E. Leiserson , Sean Lie Unbounded Transactional Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Michael R. Marty , Jesse D. Bingham , Mark D. Hill , Alan J. Hu , Milo M. K. Martin , David A. Wood Improving Multiple-CMP Systems Using Token Coherence. [Citation Graph (0, 0)][DBLP ] Conf ] Dhruba Chandra , Fei Guo , Seongbeom Kim , Yan Solihin Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Youtao Zhang , Lan Gao , Jun Yang , Xiangyu Zhang , Rajiv Gupta SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] 