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Conferences in DBLP

International Symposium on High-Performance Computer Architecture (HPCA) (hpca)
2005 (conf/hpca/2005)

  1. Fred Weber
    Trends in High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:3- [Conf]
  2. Nathan Tuck, Dean M. Tullsen
    Multithreaded Value Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:5-15 [Conf]
  3. Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez
    Checkpointed Early Load Retirement. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:16-27 [Conf]
  4. Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy
    Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:28-39 [Conf]
  5. Masaaki Kondo, Hiroshi Nakamura
    A Small, Fast and Low-Power Register File by Bit-Partitioning. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:40-49 [Conf]
  6. Krishnan Sundaresan, Nihar R. Mahapatra
    Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:51-60 [Conf]
  7. Pedro Chaparro, Grigorios Magklis, José González, Antonio González
    Distributing the Frontend for Temperature Reduction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:61-70 [Conf]
  8. Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron
    Performance, Energy, and Thermal Considerations for SMT and CMP Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:71-82 [Conf]
  9. Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg
    Tapping ZettaRAMTM for Low-Power Memory Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:83-94 [Conf]
  10. Paul Willmann, Hyong-youb Kim, Scott Rixner, Vijay S. Pai
    An Efficient Programmable 10 Gigabit Ethernet Network Interface Card. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:96-107 [Conf]
  11. José Duato, Ian Johnson, Jose Flich, Finbar Naven, Pedro Javier García, Teresa Nachiondo Frinós
    A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:108-119 [Conf]
  12. Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai Huang, Paul R. Prucnal
    Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:120-131 [Conf]
  13. Jung Ho Ahn, Mattan Erez, William J. Dally
    Scatter-Add in Data Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:132-142 [Conf]
  14. Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González
    Software Directed Issue Queue Power Reduction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:144-153 [Conf]
  15. Yan Meng, Timothy Sherwood, Ryan Kastner
    On the Limits of Leakage Power Reduction in Caches. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:154-165 [Conf]
  16. Jahangir Hasan, Ankit Jalote, T. N. Vijaykumar, Carla E. Brodley
    Heat Stroke: Power-Density-Based Denial of Service in SMT. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:166-177 [Conf]
  17. Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark
    Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:178-189 [Conf]
  18. Aamer Jaleel, Bruce L. Jacob
    Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:191-200 [Conf]
  19. Erik G. Hallnor, Steven K. Reinhardt
    A Unified Compressed Memory Hierarchy. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:201-212 [Conf]
  20. Zhichun Zhu, Zhao Zhang
    A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:213-224 [Conf]
  21. Lawrence Spracklen, Yuan Chou, Santosh G. Abraham
    Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:225-236 [Conf]
  22. Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler
    Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:238-242 [Conf]
  23. Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt
    The Soft Error Problem: An Architectural Perspective. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:243-247 [Conf]
  24. Lawrence Spracklen, Santosh G. Abraham
    Chip Multithreading: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:248-252 [Conf]
  25. Parthasarathy Ranganathan, Norman P. Jouppi
    Enterprise IT Trends and Implications for Architecture Research. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:253-256 [Conf]
  26. H. Peter Hofstee
    Power Efficient Processor Architecture and The Cell Processor. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:258-262 [Conf]
  27. Wen-mei W. Hwu, Sanjay J. Patel
    The Future of Computer Architecture Research: An Industrial Perspective. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:264- [Conf]
  28. Joshua J. Yi, Sreekumar V. Kodakara, Resit Sendag, David J. Lilja, Douglas M. Hawkins
    Characterizing and Comparing Prevailing Simulation Techniques. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:266-277 [Conf]
  29. Jeremy Lau, Stefan Schoenmackers, Brad Calder
    Transition Phase Classification and Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:278-289 [Conf]
  30. Feng Qin, Shan Lu, Yuanyuan Zhou
    SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:291-302 [Conf]
  31. Marc L. Corliss, E. Christopher Lewis, Amir Roth
    Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:303-314 [Conf]
  32. C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie
    Unbounded Transactional Memory. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:316-327 [Conf]
  33. Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M. K. Martin, David A. Wood
    Improving Multiple-CMP Systems Using Token Coherence. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:328-339 [Conf]
  34. Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihin
    Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:340-351 [Conf]
  35. Youtao Zhang, Lan Gao, Jun Yang, Xiangyu Zhang, Rajiv Gupta
    SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:352-362 [Conf]
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