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Publications of Author

1. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
   A design kit for a fully working shared memory multiprocessor on FPGA. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:219-222 [Conf]
   
2. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
   A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2007, pp:331-336 [Conf]
   
3. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
   An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2007, pp:449-450 [Conf]
   
4. Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo
   An Evolutionary Approach to Area-Time Optimization of FPGA designs. [Citation Graph (0, 0)][DBLP]
   ICSAMOS, 2007, pp:145-152 [Conf]
   
5. Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo
   Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA. [Citation Graph (0, 0)][DBLP]
   ICSAMOS, 2006, pp:107-114 [Conf]
   
6. Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
   An Interrupt Controller for FPGA-based Multiprocessors. [Citation Graph (0, 0)][DBLP]
   ICSAMOS, 2007, pp:82-87 [Conf]
   
7. Fabrizio Ferrandi, Luca Fossati, Marco Lattuada, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo
   Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs. [Citation Graph (0, 0)][DBLP]
   IESS, 2007, pp:179-192 [Conf]
   
8. 
   A Self-Reconfigurable Implementation of the JPEG Encoder. [Citation Graph (, )][DBLP]
   
   
9. 
   Lightweight DMA management mechanisms for multiprocessors on FPGA. [Citation Graph (, )][DBLP]
   
   
10. 
    Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform. [Citation Graph (, )][DBLP]
    
    
11. 
    Efficient pattern matching on GPUs for intrusion detection systems. [Citation Graph (, )][DBLP]
    
    
12. 
    Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach. [Citation Graph (, )][DBLP]
    
    
13. 
    A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications. [Citation Graph (, )][DBLP]
    
    
14. 
    A reconfigurable multiprocessor architecture for a reliable face recognition implementation. [Citation Graph (, )][DBLP]
    
    
15. 
    HW/SW methodologies for synchronization in FPGA multiprocessors. [Citation Graph (, )][DBLP]
    
    
16. 
    Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems. [Citation Graph (, )][DBLP]
    
    
17. 
    Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation. [Citation Graph (, )][DBLP]
    
    
18. 
    A multiprocessor self-reconfigurable JPEG2000 encoder. [Citation Graph (, )][DBLP]
    
    
19. 
    Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]
    
    
20. 
    Fitness inheritance in evolutionary and multi-objective high-level synthesis. [Citation Graph (, )][DBLP]