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Gianluca Palermo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Roberto Cordone, Fabrizio Ferrandi, Marco D. Santambrogio, Gianluca Palermo, Donatella Sciuto
    Using speculative computation and parallelizing techniques to improve scheduling of control based designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:898-904 [Conf]
  2. Domenico Barretta, Gianluca Palermo, Mariagiovanna Sami, Roberto Zafalon
    Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor. [Citation Graph (0, 0)][DBLP]
    CAMP, 2005, pp:265-270 [Conf]
  3. Giovanni Beltrame, Gianluca Palermo, Donatella Sciuto, Cristina Silvano
    Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:85-92 [Conf]
  4. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Power/performance hardware optimization for synchronization intensive applications in MPSoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:606-611 [Conf]
  5. Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
    Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20182-20187 [Conf]
  6. Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo
    Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:804-805 [Conf]
  7. Matteo Monchiero, Gianluca Palermo
    The Combined Perceptron Branch Predictor. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2005, pp:487-496 [Conf]
  8. Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:440-443 [Conf]
  9. Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Branch prediction techniques for low-power VLIW processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:225-228 [Conf]
  10. Gianluca Palermo, Cristina Silvano, S. Valsecchi, Vittorio Zaccaria
    A system-level methodology for fast multi-objective design space exploration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:92-95 [Conf]
  11. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    A design kit for a fully working shared memory multiprocessor on FPGA. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:219-222 [Conf]
  12. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:331-336 [Conf]
  13. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:449-450 [Conf]
  14. Guido Bertoni, Vittorio Zaccaria, Luca Breveglieri, Matteo Monchiero, Gianluca Palermo
    AES Power Attack Based on Induced Cache Miss and Countermeasure. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:586-591 [Conf]
  15. Gianluca Palermo, Cristina Silvano
    PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:521-531 [Conf]
  16. Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
    A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:249-258 [Conf]
  17. Giovanni Agosta, Gianluca Palermo, Cristina Silvano
    Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems. [Citation Graph (0, 0)][DBLP]
    SAC, 2004, pp:891-896 [Conf]
  18. Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:515-524 [Journal]
  19. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Efficient Synchronization for Embedded On-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1049-1062 [Journal]
  20. Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo
    An Evolutionary Approach to Area-Time Optimization of FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:145-152 [Conf]
  21. Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    An Interrupt Controller for FPGA-based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:82-87 [Conf]
  22. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:144-151 [Conf]
  23. Fabrizio Ferrandi, Luca Fossati, Marco Lattuada, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo
    Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:179-192 [Conf]
  24. Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo
    Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  25. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Exploration of distributed shared memory architectures for NoC-based multiprocessors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:719-732 [Journal]

  26. A Self-Reconfigurable Implementation of the JPEG Encoder. [Citation Graph (, )][DBLP]


  27. Mapping and Topology Customization Approaches for Application-Specific STNoC Designs. [Citation Graph (, )][DBLP]


  28. Lightweight DMA management mechanisms for multiprocessors on FPGA. [Citation Graph (, )][DBLP]


  29. Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform. [Citation Graph (, )][DBLP]


  30. Variability-aware robust design space exploration of chip multiprocessor architectures. [Citation Graph (, )][DBLP]


  31. Efficiency and scalability of barrier synchronization on NoC based many-core architectures. [Citation Graph (, )][DBLP]


  32. A data protection unit for NoC-based architectures. [Citation Graph (, )][DBLP]


  33. A security monitoring service for NoCs. [Citation Graph (, )][DBLP]


  34. A correlation-based design space exploration methodology for multi-processor systems-on-chip. [Citation Graph (, )][DBLP]


  35. A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications. [Citation Graph (, )][DBLP]


  36. MPSoCs run-time monitoring through Networks-on-Chip. [Citation Graph (, )][DBLP]


  37. An industrial design space exploration framework for supporting run-time resource management on multi-core systems. [Citation Graph (, )][DBLP]


  38. A reconfigurable multiprocessor architecture for a reliable face recognition implementation. [Citation Graph (, )][DBLP]


  39. Energy-performance design space exploration in SMT architectures exploiting selective load value predictions. [Citation Graph (, )][DBLP]


  40. Application-Specific Topology Design Customization for STNoC. [Citation Graph (, )][DBLP]


  41. A Modular Approach to Model Heterogeneous MPSoC at Cycle Level. [Citation Graph (, )][DBLP]


  42. Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration. [Citation Graph (, )][DBLP]


  43. Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip. [Citation Graph (, )][DBLP]


  44. Robust optimization of SoC architectures: A multi-scenario approach. [Citation Graph (, )][DBLP]


  45. HW/SW methodologies for synchronization in FPGA multiprocessors. [Citation Graph (, )][DBLP]


  46. Implementation of a reconfigurable data protection module for NoC-based MPSoCs. [Citation Graph (, )][DBLP]


  47. A multiprocessor self-reconfigurable JPEG2000 encoder. [Citation Graph (, )][DBLP]


  48. An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods. [Citation Graph (, )][DBLP]


  49. Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques. [Citation Graph (, )][DBLP]


  50. Fitness inheritance in evolutionary and multi-objective high-level synthesis. [Citation Graph (, )][DBLP]


  51. An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints. [Citation Graph (, )][DBLP]


  52. A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip. [Citation Graph (, )][DBLP]


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