The SCEAS System
Navigation Menu

Conferences in DBLP

2007 (conf/iess/2007)

  1. Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten
    Requirements and Concepts for Transaction Level Assertion Refinement. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:1-14 [Conf]
  2. Bernhard Rieder, Ingomar Wenzel, Klaus Steinhammer, Peter P. Puschner
    Using a Runtime Measurement Device with Measurement-Based WCET Analysis. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:15-26 [Conf]
  3. Pierre Niang, Thierry Grandpierre, Mohamed Akil
    Implementing Real-Time Algorithms by using the AAA Prototyping Methodology. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:27-36 [Conf]
  4. Karsten Albers, Frank Bodmann, Frank Slomka
    Run-Time efficient Feasibility Analysis of Uni-Processor Systems with Static Priorities. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:37-46 [Conf]
  5. Henning Zabel, Achim Rettberg, Alexander Krupp
    Approach for a Formal Verification of a Bit-serial Pipelined Architecture. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:47-56 [Conf]
  6. Razvan Racu, Arne Hamann, Rolf Ernst
    Automotive System Optimization using Sensitivity Analysis. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:57-70 [Conf]
  7. Richard Anthony, Achim Rettberg, De-Jiu Chen, Isabell Jahnich, Gerrit de Boer, Cecilia Ekelin
    Towards a Dynamically Reconfigurable Automotive Control System Architecture. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:71-84 [Conf]
  8. Christian Wawersich, Michael Stilkerich, Wolfgang Schröder-Preikschat
    An OSEK/VDX-based Multi-JVM for Automotive Appliances. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:85-96 [Conf]
  9. Isabell Jahnich, Achim Rettberg
    Towards Dynamic Load Balancing for Distributed Embedded Automotive Systems. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:97-106 [Conf]
  10. Jelena Trajkovic, Daniel Gajski
    Automatic Data Path Generation from C code for Custom Processors. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:107-120 [Conf]
  11. Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita
    Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:121-134 [Conf]
  12. Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski
    An Interactive Design Environment for C-based High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:135-144 [Conf]
  13. Scott Sirowy, Frank Vahid
    Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:145-154 [Conf]
  14. Lars Middendorf, Felix Mühlbauer, Georg Umlauf, Christophe Bobda
    Embedded Vertex Shader in FPGA. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:155-164 [Conf]
  15. Alexander Viehl, Markus Schwarz, Oliver Bringmann, Wolfgang Rosenstiel
    A Hybrid Approach for System-Level Design Evaluation. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:165-178 [Conf]
  16. Fabrizio Ferrandi, Luca Fossati, Marco Lattuada, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo
    Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:179-192 [Conf]
  17. Pramod Chandraiah, Rainer Dömer
    An Interactive Model Re-Coder for Efficient SoC Specification. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:193-206 [Conf]
  18. M. B. Abdelhalim, A. E. Salama, S. E.-D. Habib
    Constrained and Unconstrained Hardware-Software Partitioning using Particle Swarm Optimization Technique. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:207-220 [Conf]
  19. Edison Pignaton Freitas, Marco A. Wehrmeister, Carlos Eduardo Pereira, Flávio Rech Wagner, Elias T. Silva, Fabiano Costa Carvalho
    Using Aspect-Oriented Concepts in the Requirements Analysis of Distributed Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:221-230 [Conf]
  20. Mike Olivarez, Brian Beasley
    Smart Speed TechnologyTM. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:231-240 [Conf]
  21. Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada
    Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:241-254 [Conf]
  22. Noureddine Chabini, Wayne Wolf
    Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:255-268 [Conf]
  23. Mark Panahi, Trevor Harmon, Juan A. Colmenares, Shruti Gorappa, Raymond Klefstad
    Identification and Removal of Program Slice Criteria for Code Size Reduction in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:269-278 [Conf]
  24. Timo Kerstan, Simon Oberthür
    Configurable Hybridkernel for Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:279-288 [Conf]
  25. Gunar Schirner, Gautam Sachdeva, Andreas Gerstlauer, Rainer Dömer
    Embedded Software Development in a System-Level Design Flow. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:289-298 [Conf]
  26. Ilya Issenin, Nikil Dutt
    Data Reuse Driven Memory and Network-On-Chip Co-Synthesis. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:299-312 [Conf]
  27. Rauf Salimi Khaligh, Martin Radetzki
    Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:313-324 [Conf]
  28. Klaus Steinhammer, Astrit Ademaj
    Hardware Implementation of the Time-Triggered Ethernet Controller. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:325-338 [Conf]
  29. Roman Obermaisser, Hermann Kopetz, Christian El Salloum, Bernhard Huber
    Error Containment in the Time-Triggered System-On-a-Chip Architecture. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:339-352 [Conf]
  30. Leonel Sousa, Moisés Simões Piedade, J. Germano, Teresa Mendes de Almeida, Paulo Alexandre Crisóstomo Lopes, Filipe Cardoso, Paulo Freitas
    Generic Architecture Designed for Biomedical Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:353-362 [Conf]
  31. Dirk Jansen, Nidal Fawaz, Daniel Bau, Marc Durrenberger
    A Small High Performance Microprocessor Core Sirius for Embedded Low Power Designs, Demonstrated in a Medical Mass Application of an Electronic Pill(EPill®). [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:363-372 [Conf]
  32. Dominik Murr, Felix Mühlbauer, Falko Dressler, Christophe Bobda
    Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:373-386 [Conf]
  33. Meik Felser, Rüdiger Kapitza, Jürgen Kleinöder, Wolfgang Schröder-Preikschat
    Dynamic Software Update of Resource-Constrained Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:387-400 [Conf]
  34. Lucas Francisco Wanner, Augusto Born de Oliveira, Antônio Augusto Fröhlich
    Configurable Medium Access Control for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:401-410 [Conf]
  35. Augusto Born de Oliveira, Lucas Francisco Wanner, Pierre Kuonen, Antônio Augusto Fröhlich
    Integrating Wireless Sensor Networks and the Grid through POP-C++. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:411-420 [Conf]
  36. K. H. (Kane) Kim
    Modeling of Software-Hardware Complexes. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:421- [Conf]
  37. Nikil Dutt
    Modeling of Software-Hardware Complexes. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:423-425 [Conf]
  38. K. H. (Kane) Kim
    Enhancing a Real-Time Distributed Computing Component Model through Cross-Fertilization. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:427-430 [Conf]
  39. Hermann Kopetz
    Modeling of Software-Hardware Complexes. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:431-432 [Conf]
  40. Franz-Josef Rammig
    Software-Hardware Complexes: Towards Flexible Borders. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:433-435 [Conf]
  41. Flávio Rech Wagner, Luigi Carro
    Embedded SW Design Space Exploration and Automation using UML-Based Tools. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:437-440 [Conf]
  42. Roozbeh Jafari, Soheil Ghiasi, Majid Sarrafzadeh
    Medical Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:441-444 [Conf]
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002