Conferences in DBLP
(iess) Wolfgang Ecker , Volkan Esen , Thomas Steininger , Michael Velten Requirements and Concepts for Transaction Level Assertion Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Rieder , Ingomar Wenzel , Klaus Steinhammer , Peter P. Puschner Using a Runtime Measurement Device with Measurement-Based WCET Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Niang , Thierry Grandpierre , Mohamed Akil Implementing Real-Time Algorithms by using the AAA Prototyping Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Karsten Albers , Frank Bodmann , Frank Slomka Run-Time efficient Feasibility Analysis of Uni-Processor Systems with Static Priorities. [Citation Graph (0, 0)][DBLP ] Conf ] Henning Zabel , Achim Rettberg , Alexander Krupp Approach for a Formal Verification of a Bit-serial Pipelined Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Razvan Racu , Arne Hamann , Rolf Ernst Automotive System Optimization using Sensitivity Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Anthony , Achim Rettberg , De-Jiu Chen , Isabell Jahnich , Gerrit de Boer , Cecilia Ekelin Towards a Dynamically Reconfigurable Automotive Control System Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Wawersich , Michael Stilkerich , Wolfgang Schröder-Preikschat An OSEK/VDX-based Multi-JVM for Automotive Appliances. [Citation Graph (0, 0)][DBLP ] Conf ] Isabell Jahnich , Achim Rettberg Towards Dynamic Load Balancing for Distributed Embedded Automotive Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jelena Trajkovic , Daniel Gajski Automatic Data Path Generation from C code for Custom Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Shanghua Gao , Kenshu Seto , Satoshi Komatsu , Masahiro Fujita Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Dongwan Shin , Andreas Gerstlauer , Rainer Dömer , Daniel D. Gajski An Interactive Design Environment for C-based High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Sirowy , Frank Vahid Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Lars Middendorf , Felix Mühlbauer , Georg Umlauf , Christophe Bobda Embedded Vertex Shader in FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Viehl , Markus Schwarz , Oliver Bringmann , Wolfgang Rosenstiel A Hybrid Approach for System-Level Design Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrizio Ferrandi , Luca Fossati , Marco Lattuada , Gianluca Palermo , Donatella Sciuto , Antonino Tumeo Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Pramod Chandraiah , Rainer Dömer An Interactive Model Re-Coder for Efficient SoC Specification. [Citation Graph (0, 0)][DBLP ] Conf ] M. B. Abdelhalim , A. E. Salama , S. E.-D. Habib Constrained and Unconstrained Hardware-Software Partitioning using Particle Swarm Optimization Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Edison Pignaton Freitas , Marco A. Wehrmeister , Carlos Eduardo Pereira , Flávio Rech Wagner , Elias T. Silva , Fabiano Costa Carvalho Using Aspect-Oriented Concepts in the Requirements Analysis of Distributed Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Olivarez , Brian Beasley Smart Speed TechnologyTM . [Citation Graph (0, 0)][DBLP ] Conf ] Gang Zeng , Hiroyuki Tomiyama , Hiroaki Takada Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services. [Citation Graph (0, 0)][DBLP ] Conf ] Noureddine Chabini , Wayne Wolf Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Panahi , Trevor Harmon , Juan A. Colmenares , Shruti Gorappa , Raymond Klefstad Identification and Removal of Program Slice Criteria for Code Size Reduction in Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Timo Kerstan , Simon Oberthür Configurable Hybridkernel for Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Gunar Schirner , Gautam Sachdeva , Andreas Gerstlauer , Rainer Dömer Embedded Software Development in a System-Level Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Ilya Issenin , Nikil Dutt Data Reuse Driven Memory and Network-On-Chip Co-Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Rauf Salimi Khaligh , Martin Radetzki Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Steinhammer , Astrit Ademaj Hardware Implementation of the Time-Triggered Ethernet Controller. [Citation Graph (0, 0)][DBLP ] Conf ] Roman Obermaisser , Hermann Kopetz , Christian El Salloum , Bernhard Huber Error Containment in the Time-Triggered System-On-a-Chip Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Leonel Sousa , Moisés Simões Piedade , J. Germano , Teresa Mendes de Almeida , Paulo Alexandre Crisóstomo Lopes , Filipe Cardoso , Paulo Freitas Generic Architecture Designed for Biomedical Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Jansen , Nidal Fawaz , Daniel Bau , Marc Durrenberger A Small High Performance Microprocessor Core Sirius for Embedded Low Power Designs, Demonstrated in a Medical Mass Application of an Electronic Pill(EPill®). [Citation Graph (0, 0)][DBLP ] Conf ] Dominik Murr , Felix Mühlbauer , Falko Dressler , Christophe Bobda Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes. [Citation Graph (0, 0)][DBLP ] Conf ] Meik Felser , Rüdiger Kapitza , Jürgen Kleinöder , Wolfgang Schröder-Preikschat Dynamic Software Update of Resource-Constrained Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Lucas Francisco Wanner , Augusto Born de Oliveira , Antônio Augusto Fröhlich Configurable Medium Access Control for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Augusto Born de Oliveira , Lucas Francisco Wanner , Pierre Kuonen , Antônio Augusto Fröhlich Integrating Wireless Sensor Networks and the Grid through POP-C++. [Citation Graph (0, 0)][DBLP ] Conf ] K. H. (Kane) Kim Modeling of Software-Hardware Complexes. [Citation Graph (0, 0)][DBLP ] Conf ] Nikil Dutt Modeling of Software-Hardware Complexes. [Citation Graph (0, 0)][DBLP ] Conf ] K. H. (Kane) Kim Enhancing a Real-Time Distributed Computing Component Model through Cross-Fertilization. [Citation Graph (0, 0)][DBLP ] Conf ] Hermann Kopetz Modeling of Software-Hardware Complexes. [Citation Graph (0, 0)][DBLP ] Conf ] Franz-Josef Rammig Software-Hardware Complexes: Towards Flexible Borders. [Citation Graph (0, 0)][DBLP ] Conf ] Flávio Rech Wagner , Luigi Carro Embedded SW Design Space Exploration and Automation using UML-Based Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Roozbeh Jafari , Soheil Ghiasi , Majid Sarrafzadeh Medical Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] 