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Publications of Author

1. Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
   A new method for constructing IP level power model based on power sensitivity. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:135-140 [Conf]
   
2. Wen-Zen Shen, Jing-Yuan Lin, Fong-Wen Wang
   Transistor reordering rules for power reduction in CMOS gates. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1995, pp:- [Conf]
   
3. Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin
   Integration, Verification and Layout of a Complex Multimedia SOC. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:1116-1117 [Conf]
   
4. Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen
   A cell-based power estimation in CMOS combinational circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1994, pp:304-309 [Conf]
   
5. Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
   A power modeling and characterization method for the CMOS standard cell library. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1996, pp:400-404 [Conf]
   
6. Jing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
   A power modeling and characterization method for macrocells using structure information. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1997, pp:502-506 [Conf]
   
7. Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin
   Integration, Verification and Layout of a Complex Multimedia SOC [Citation Graph (0, 0)][DBLP]
   CoRR, 2007, v:0, n:, pp:- [Journal]
   
8. Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
   A structure-oriented power modeling technique for macrocells. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:380-391 [Journal]
   
9. 
   Experiences of low power design implementation and verification. [Citation Graph (, )][DBLP]
   
   
10. 
    DFM/DFY practices during physical designs for timing, signal integrity, and power. [Citation Graph (, )][DBLP]