Conferences in DBLP
Ruchir Puri , Andrew Bjorksten , Thomas E. Rosser Logic optimization by output phase assignment in dynamic logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoqing Wen , Kewal K. Saluja A new method towards achieving global optimality in technology mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Juinn-Dar Huang , Jing-Yang Jou , Wen-Zen Shen An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Guowu Zheng , Qi-Jun Zhang , Michel S. Nakhla , Ramachandra Achar An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data. [Citation Graph (0, 0)][DBLP ] Conf ] Steven D. Corey , Andrew T. Yang Automatic netlist extraction for measurement-based characterization of off-chip interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Kei Masuko , Sudhakar Muddu Analytical delay models for VLSI interconnects under ramp input. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Ping Chen , Hai Zhou , D. F. Wong Optimal non-uniform wire-sizing under the Elmore delay model. [Citation Graph (0, 0)][DBLP ] Conf ] Takumi Okamoto , Jason Cong Buffered Steiner tree construction with wire sizing for interconnect layout optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Daksh Lehther , Sachin S. Sapatnekar Clock tree synthesis for multi-chip modules. [Citation Graph (0, 0)][DBLP ] Conf ] Wanlin Cao , Dhiraj K. Pradhan Sequential redundancy identification using recursive learning. [Citation Graph (0, 0)][DBLP ] Conf ] Ismed Hartanto , Vamsi Boppana , W. Kent Fuchs Identification of unsettable flip-flops for partial scan and faster ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth M. Rudnick , Janak H. Patel Simulation-based techniques for dynamic test sequence compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Woohyuk Lee , Abelardo Pardo , Jae-Young Jang , Gary D. Hachtel , Fabio Somenzi Tearing based automatic abstraction for CTL model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Iwashita , Tsuneo Nakata , Fumiyasu Hirose CTL model checking based on forward state traversal. [Citation Graph (0, 0)][DBLP ] Conf ] Dhiraj K. Pradhan , Debjyoti Paul , Mitrajit Chatterjee VERILAT: verification using logic augmentation and transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Youngsoo Shin , Kiyoung Choi Software synthesis through task decomposition by dependency analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Zhao , Christos A. Papachristou Synthesis of reusable DSP cores based on multiple behaviors. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Leupers , Peter Marwedel Algorithms for address assignment in DSP code generation. [Citation Graph (0, 0)][DBLP ] Conf ] Hakan Yalcin , John P. Hayes , Karem A. Sakallah An approximate timing analysis method for datapath circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Vinod Narayanan , Barbara A. Chappell , Bruce M. Fleischer Static timing analysis for self resetting circuits. [Citation Graph (0, 0)][DBLP ] Conf ] David Van Campenhout , Trevor N. Mudge , Karem A. Sakallah Timing verification of sequential domino circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gunther Lehmann , Bernhard Wunder , Klaus D. Müller-Glaser Basic concepts for an HDL reverse engineering tool-set. [Citation Graph (0, 0)][DBLP ] Conf ] Eric W. Johnson , Jay B. Brockman Sensitivity analysis of iterative design processes. [Citation Graph (0, 0)][DBLP ] Conf ] Richard C. Ho , Mark Horowitz Validation coverage analysis for complex digital designs. [Citation Graph (0, 0)][DBLP ] Conf ] Hsiao-Ping Juan , Daniel Gajski , Viraphol Chaiyakul Clock-driven performance optimization in interactive behavioral synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Raghunathan , Sujit Dey , Niraj K. Jha Register-transfer level estimation techniques for switching activity and power consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Renu Mehra , Jan M. Rabaey Exploiting regularity for low-power design. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew R. Conn , Paula K. Coulman , Ruud A. Haring , Gregory L. Morrill , Chandramouli Visweswariah Optimization of custom MOS circuits by transistor sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Lei He An efficient approach to simultaneous transistor and interconnect sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Edoardo Charbon , Paolo Miliozzi , Enrico Malavasi , Alberto L. Sangiovanni-Vincentelli Generalized constraint generation in the presence of non-deterministic parasitics. [Citation Graph (0, 0)][DBLP ] Conf ] Shantanu Dutt , Wenyong Deng VLSI circuit partitioning by cluster-removal using iterative improvement techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Y. Zien , Martine D. F. Schlag , Pak K. Chan Multi-level spectral hypergraph partitioning with arbitrary vertex sizes. [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Kei Mak , D. F. Wong Minimum replication min-cut partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Alok Agrawal , Alexander Saldanha , Luciano Lavagno , Alberto L. Sangiovanni-Vincentelli Compact and complete test set generation for multiple stuck-faults. [Citation Graph (0, 0)][DBLP ] Conf ] João P. Marques Silva , Karem A. Sakallah GRASP - a new search algorithm for satisfiability. [Citation Graph (0, 0)][DBLP ] Conf ] Hisashi Kondo , Kwang-Ting Cheng Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Edward A. Lee , Alberto L. Sangiovanni-Vincentelli Comparing models of computation. [Citation Graph (0, 0)][DBLP ] Conf ] N. P. van der Meijs , T. Smedes Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeru Yamashita , Hiroshi Sawada , Akira Nagoya A new method to express functional permissibilities for LUT based FPGAs and its applications. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chieh Chang , Lukas P. P. P. van Ginneken , Malgorzata Marek-Sadowska Fast Boolean optimization by rewiring. [Citation Graph (0, 0)][DBLP ] Conf ] Qi Wang , Sarma B. K. Vrudhula Multi-level logic optimization for low power using local logic transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Roland W. Freund , Peter Feldmann Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Luis Miguel Silveira , Mattan Kamon , Ibrahim M. Elfadel , Jacob White A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Feldmann , Jaijeet S. Roychowdhury Computation of circuit waveform envelopes using an efficient, matrix-decomposed harmonic balance algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Tianxiong Xue , Ernest S. Kuh , Dongsheng Wang Post global routing crosstalk risk estimation and reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Zhou , D. F. Wong An optimal algorithm for river routing with crosstalk constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Joe G. Xi , Wayne Wei-Ming Dai Jitter-tolerant clock routing in two-phase synchronous systems. [Citation Graph (0, 0)][DBLP ] Conf ] Frank F. Hsu , Elizabeth M. Rudnick , Janak H. Patel Enhancing high-level control-flow for improved testability. [Citation Graph (0, 0)][DBLP ] Conf ] Indradeep Ghosh , Anand Raghunathan , Niraj K. Jha A design for testability technique for RTL circuits using control/data flow extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Hans-Joachim Wunderlich , Gundolf Kiefer Bit-flipping BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Pranav Ashar , Aarti Gupta , Sharad Malik Using complete-1-distinguishability for FSM equivalence checking. [Citation Graph (0, 0)][DBLP ] Conf ] Gianpiero Cabodi , Paolo Camurati , Stefano Quer Improved reachability analysis of large finite state machines. [Citation Graph (0, 0)][DBLP ] Conf ] Yirng-An Chen , Randal E. Bryant ACV: an arithmetic circuit verifier. [Citation Graph (0, 0)][DBLP ] Conf ] Hans T. Heineken , Wojciech Maly Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Felt , Stefano Zanella , Carlo Guardiani , Alberto L. Sangiovanni-Vincentelli Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Hong II , Weikai Sun , Zhenhai Zhu , Hao Ji , Ben Song , Wayne Wei-Ming Dai A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Brand , Chandramouli Visweswariah Inaccuracies in power estimation during logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Vittal , Hein Ha , Forrest Brewer , Malgorzata Marek-Sadowska Clock skew optimization for ground bounce control. [Citation Graph (0, 0)][DBLP ] Conf ] Jiing-Yuan Lin , Wen-Zen Shen , Jing-Yang Jou A power modeling and characterization method for the CMOS standard cell library. [Citation Graph (0, 0)][DBLP ] Conf ] Kyosun Kim , Ramesh Karri , Miodrag Potkonjak Heterogeneous built-in resiliency of application specific programmable processors. [Citation Graph (0, 0)][DBLP ] Conf ] William J. Schilp , Peter M. Maurer Unit delay simulation with the inversion algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Abhijit Ghosh , Kurt Keutzer An observability-based code coverage metric for functional simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Ellen Sentovich , Horia Toma , Gérard Berry Latch optimization in circuits generated from high-level descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Samit Chaudhuri , Michael Quayle Synthesis using sequential functional modules (SFMs). [Citation Graph (0, 0)][DBLP ] Conf ] Ki-Seok Chung , Rajesh K. Gupta , C. L. Liu An algorithm for synthesis of system-level interface circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chad Young , Giorgio Casinovi , Jonathan Fowler , Paul Kerstetter An algorithm for power estimation in switched-capacitor circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Edoardo Charbon , Ranjit Gharpurey , Alberto L. Sangiovanni-Vincentelli , Robert G. Meyer Semi-analytical techniques for substrate characterization in the design of mixed-signal ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Iasson Vassiliou , Henry Chang , Alper Demir , Edoardo Charbon , Paolo Miliozzi , Alberto L. Sangiovanni-Vincentelli A video driver system designed using a top-down, constraint-driven methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Behrens , Klaus Harbich , Erich Barke Hierarchical partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Takayuki Yamanouchi , Kazuo Tamakashi , Takashi Kambe Hybrid floorplanning based on partial clustering and module restructuring. [Citation Graph (0, 0)][DBLP ] Conf ] Shigetoshi Nakatake , Kunihiro Fujiyoshi , Hiroshi Murata , Yoji Kajitani Module placement on BSG-structure and IC layout applications. [Citation Graph (0, 0)][DBLP ] Conf ] Mukund Sivaraman , Andrzej J. Strojwas Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. [Citation Graph (0, 0)][DBLP ] Conf ] Keerthi Heragu , Janak H. Patel , Vishwani D. Agrawal SIGMA: a simulator for segment delay faults. [Citation Graph (0, 0)][DBLP ] Conf ] Minesh B. Amin , Bapiraju Vinnakota Zamlog: a parallel algorithm for fault simulation based on Zambezi. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon W. Roberts Metrics, techniques and recent developments in mixed-signal testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. Shepard , Vinod Narayanan Noise in deep submicron digital design. [Citation Graph (0, 0)][DBLP ] Conf ] David C. Ku , James A. Rowson Intranets and EDA: impact, application, and technology. [Citation Graph (0, 0)][DBLP ] Conf ] Desmond Kirkpatrick , Alberto L. Sangiovanni-Vincentelli Digital sensitivity: predicting signal interaction using functional analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Woods , Giorgio Casinovi Efficient solution of systems of Boolean equations. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Narayan , Jawahar Jain , Masahiro Fujita , Alberto L. Sangiovanni-Vincentelli Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. [Citation Graph (0, 0)][DBLP ] Conf ] Jun-Fa Mao , Janet Meiling Wang , Ernest S. Kuh Simulation and sensitivity analysis of transmission line circuits by the characteristics method. [Citation Graph (0, 0)][DBLP ] Conf ] Mustafa Celik , Andreas C. Cangellaris A general dispersive multiconductor transmission line model for interconnect simulation in SPICE. [Citation Graph (0, 0)][DBLP ] Conf ] Sharad Kapur , David E. Long , Jaijeet S. Roychowdhury Efficient time-domain simulation of frequency-dependent elements. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Shun Ding , Cheng-Ta Hsieh , Qing Wu , Massoud Pedram Stratified random sampling for power estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Ta Hsieh , Qing Wu , Chih-Shun Ding , Massoud Pedram Statistical sampling and regression analysis for RT-level power evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis J. Ciplickas , Ronald A. Rohrer Expected current distributions for CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su , Yue-Tsang Chen , Shyh-Jye Jou , Yuan-Tzu Ting Metrology for analog module testing using analog testability bus. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelo Lubaszewski , Salvador Mir , Leandro Pulz ABILBO: Analog BuILt-in Block Observer. [Citation Graph (0, 0)][DBLP ] Conf ] Walter M. Lindermeir Design of robust test criteria in analog testing. [Citation Graph (0, 0)][DBLP ] Conf ] Balakrishnan Iyer , Maciej J. Ciesielski Metamorphosis: state assignment by retiming and re-encoding. [Citation Graph (0, 0)][DBLP ] Conf ] Vigyan Singhal , Sharad Malik , Robert K. Brayton The case for retiming with explicit reset circuitry. [Citation Graph (0, 0)][DBLP ] Conf ] Harm Arts , Michel R. C. M. Berkelaar , C. A. J. van Eijk Polarized observability don't cares. [Citation Graph (0, 0)][DBLP ] Conf ] Inki Hong , Miodrag Potkonjak Power optimization in disk-based real-time application specific systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Jong Fang , Allen C.-H. Wu A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Shin-ichi Minato Generation of BDDs from hardware algorithm descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Vaughn Betz , Jonathan Rose Directional bias and non-uniformity in FPGA global routing architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Avaneendra Gupta , John P. Hayes Width minimization of two-dimensional CMOS cells using integer programming. [Citation Graph (0, 0)][DBLP ] Conf ] Man-Fai Yu , Joel Darnauer , Wayne Wei-Ming Dai Interchangeable pin routing with application to package layout. [Citation Graph (0, 0)][DBLP ] Conf ] Xiao-Tao Chen , Fabrizio Lombardi A coloring approach to the structural diagnosis of interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi Boppana , W. Kent Fuchs Integrated fault diagnosis targeting reduced simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Kanad Chakraborty , Pinaki Mazumder An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Maly , Hans T. Heineken , Jitendra Khare , Pranab K. Nag Design for manufacturability in submicron domain. [Citation Graph (0, 0)][DBLP ] Conf ] Ralph H. J. M. Otten , Lukas P. P. P. van Ginneken , Narendra V. Shenoy Embedded tutorial: Speed - new paradigms in design for performance. [Citation Graph (0, 0)][DBLP ] Conf ] 