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Yue-Tsang Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chauchin Su, Yi-Ren Cheng, Yue-Tsang Chen, Shing Tenchen
    Analog signal metrology for mixed signal ICs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:194-0 [Conf]
  2. Chauchin Su, Yue-Tsang Chen, Chung-Len Lee
    Analog Metrology and Stimulus Selection in a Noisy Environment. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:233-238 [Conf]
  3. Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee
    All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:527-0 [Conf]
  4. Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting
    Metrology for analog module testing using analog testability bus. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:594-599 [Conf]
  5. Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
    Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:499-508 [Conf]
  6. Chauchin Su, Shung-Won Jeng, Yue-Tsang Chen
    Boundary scan BIST methodology for reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:774-783 [Conf]
  7. Yue-Tsang Chen, Chauchin Su
    Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:260-265 [Conf]
  8. Chauchin Su, Yue-Tsang Chen
    Crosstalk Effect Removal for Analog Measurement in Analog Test Bus. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:403-410 [Conf]
  9. Chauchin Su, Yue-Tsang Chen, Shenshung Chiang
    Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2000, v:16, n:5, pp:767-781 [Journal]
  10. Chauchin Su, Yue-Tsang Chen
    Intrinsic response extraction for the removal of the parasiticeffects in analog test buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:437-445 [Journal]
  11. Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
    Intrinsic response for analog module testing using an analog testability bus. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:2, pp:226-243 [Journal]

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