Conferences in DBLP
Abhijit Jas , C. V. Krishna , Nur A. Touba Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas Kay , Samiha Mourad Compression Technique for Interactive BIST Application. [Citation Graph (0, 0)][DBLP ] Conf ] Mihalis Psarakis , Antonis M. Paschalis , Nektarios Kranitis , Dimitris Gizopoulos , Yervant Zorian Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-Mo James Li , Edward J. McCluskey Diagnosis of Tunneling Opens. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh C. Tekumalla , Srikanth Venkataraman , Jayabrata Ghosh-Dastidar On Diagnosing Path Delay Faults in an At-Speed Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Yu Huang On Improving the Accuracy Of Multiple Defect Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Anshuman Chandra , Krishnendu Chakrabarty Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression. [Citation Graph (0, 0)][DBLP ] Conf ] A. Morozov , Michael Gössel , Krishnendu Chakrabarty , Bhargab B. Bhattacharya Design of Parameterizable Error-Propagating Space Compactors for Response Observation. [Citation Graph (0, 0)][DBLP ] Conf ] Aiman El-Maleh , Esam Khan , Saif al Zahir A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Richard M. Chou , Kewal K. Saluja Testable Sequential Circuit Design: A Partition and Resynthesis Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammad Nummer , Manoj Sachdev A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency. [Citation Graph (0, 0)][DBLP ] Conf ] Kelly A. Ockunzzi , Christos A. Papachristou Breaking Correlation to Improve Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Xiang , Yi Xu Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Ilia Polian , Bernd Becker Multiple Scan Chain Design for Two-Pattern Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Dilip K. Bhavsar Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro J. Yamaguchi , Masahiro Ishida , Mani Soma , David Halter , Rajesh Raina , Jim Nissen A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Attarha , Mehrdad Nourani Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoyun Sun , Bapiraju Vinnakota Current Measurement for Dynamic Idd Test. [Citation Graph (0, 0)][DBLP ] Conf ] Enamul Amyeen , W. Kent Fuchs , Irith Pomeranz , Vamsi Boppana Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Julia Dushina , Mike Benjamin , Daniel Geist Semi-Formal Test Generation for a Block of Industrial DSP. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Zenteno , Víctor H. Champac Resistive Opens in a Class of CMOS Latches: Analysis and DFT. [Citation Graph (0, 0)][DBLP ] Conf ] Chintan Patel , Jim Plusquellic A Process and Technology-Tolerant IDDQ Method for IC Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Bottoms , Jim Chung , Bernd Koenemann , Glenn Shirley , Lisa Spainhower Guaranteeing Quality throughout the Product Life Cycle: On-Line Test and Repair to the Rescue. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Rodgers ITRS Test Chapter 2001: We'll Tell You What We're Doing, You Tell Us What We Should Be Doing. [Citation Graph (0, 0)][DBLP ] Conf ] Tek Jau Tan , Chung-Len Lee Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Giani , Shuo Sheng , Michael S. Hsiao , Vishwani D. Agrawal Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoliang Bai , Sujit Dey High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Subhasish Mitra , Edward J. McCluskey Design Diversity for Concurrent Error Detection in Sequential Logic Circuts. [Citation Graph (0, 0)][DBLP ] Conf ] Egor S. Sogomonyan , A. A. Morosov , Jan Rzeha , Michael Gössel , Adit D. Singh Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging. [Citation Graph (0, 0)][DBLP ] Conf ] Subhasish Mitra , Edward J. McCluskey Design of Redundant Systems Protected Against Common-Mode Failures. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Reng Huang , Madhu K. Iyer , Kwang-Ting Cheng A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Cheng Lai , Jing-Reng Huang , Kwang-Ting (Tim) Cheng Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Benoît Charlot , Salvador Mir , Fabien Parrain , Bernard Courtois Electrically Induced Stimuli For MEMS Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Gh. Mohammad , Kewal K. Saluja Flash Memory Disturbances: Modeling and Test. [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Liang Cheng , Ming-Fu Tsai , Cheng-Wen Wu Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Sultan M. Al-Harbi , Sandeep K. Gupta An Efficient Methodology for Generating Optimal and Uniform March Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Ozgur Sinanoglu , Alex Orailoglu RT-level Fault Simulation Based on Symbolic Propagation. [Citation Graph (0, 0)][DBLP ] Conf ] Yiorgos Makris , Vishal Patel , Alex Orailoglu Efficient Transparency Extraction and Utilization in Hierarchical Test. [Citation Graph (0, 0)][DBLP ] Conf ] Magdy S. Abadir , Juhong Zhu , Li-C. Wang Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Yue-Tsang Chen , Chauchin Su Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization. [Citation Graph (0, 0)][DBLP ] Conf ] Florence Azaïs , Serge Bernard , Yves Bertrand , Xavier Michel , Michel Renovell A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo J. Peralías , Gloria Huertas , Adoración Rueda , José L. Huertas Self-Testable Pipelined ADC with Low Hardware Overhead. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Chung , N. Derhacobian , Jean Gasiot , Michael Nicolaidis , David Towne , R. Velazco Soft Errors and Tolerance for Soft Errors. [Citation Graph (0, 0)][DBLP ] Conf ] Tracy Larrabee , Jon Colbum Yield Optimization and Its Relation to Test. [Citation Graph (0, 0)][DBLP ] Conf ] Magdy S. Abadir , Scott Davidson , Vijay Nagasamy , Dhiraj K. Pradhan , Prab Varma ATPG for Design Errors-Is It Possible? [Citation Graph (0, 0)][DBLP ] Conf ] I. de Paúl , M. Rosales , B. Alorda , Jaume Segura , Charles F. Hawkins , Jerry M. Soden Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. [Citation Graph (0, 0)][DBLP ] Conf ] John T. Chen , Wojciech Maly , Janusz Rajski , Omar Kebichi , Jitendra Khare Enabling Embedded Memory Diagnosis via Test Response Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Niggemeyer , Elizabeth M. Rudnick Automatic Generation of Diagnostic March Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Loïs Guiller , Christian Landrault , Serge Pravossoudovitch , Hans-Joachim Wunderlich A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Tobias Schüle , Albrecht P. Stroele Test Scheduling for Minimal Energy Consumption under Power Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Ranganathan Sankaralingam , Nur A. Touba , Bahram Pouya Reducing Power Dissipation during Test Using Scan Chain Disable. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas S. Barnett , Adit D. Singh , Victor P. Nelson Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Athar Khalil , Chin-Long Wey High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] Chao-Wen Tseng , Ray Chen , Edward J. McCluskey , Phil Nigh MINVDD Testing for Weak CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Emil Gizdarski , Hideo Fujiwara SPIRIT: A Highly Robust Combinational Test Generation Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On the Use of Fault Dominance in n-Detection Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Shing Chang , Sandeep K. Gupta , Melvin A. Breuer Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. [Citation Graph (0, 0)][DBLP ] Conf ] Vikram Iyengar , Krishnendu Chakrabarty Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] José Pineda de Gyvez , Eric van de Wetering Average Leakage Current Estimation of CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jiun-Lang Huang , Kwang-Ting Cheng An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. [Citation Graph (0, 0)][DBLP ] Conf ] Ginette Monté , Bernard Antaki , Serge Patenaude , Yvon Savaria , Claude Thibeault , Pieter M. Trouborst Tools for the Characterization of Bipolar CML Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Keerthi Heragu , Manish Sharma , Rahul Kundu , R. D. (Shawn) Blanton Testing of Dynamic Logic Circuits Based on Charge Sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Chao-Wen Tseng , Subhasish Mitra , Edward J. McCluskey , Scott Davidson An Evaluation of Pseudo Random Testing for Detecting Real Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Dwayne Burek , Garen Darbinyan , Rohit Kapur , Maurice Lousberg , Teresa L. McLaurin , Mike Ricchetti IP and Automation to Support IEEE P1500. [Citation Graph (0, 0)][DBLP ] Conf ] Pete O'Neill , Ron Richmond , Mike Tripp , Barbara Vasquez , Art Wager , Zeev Weinberg Reliability Beyond GHz. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Chang , Steve Dollens , Gordon Roberts , Charles E. Stroud , Mani Soma , Jacob A. Abraham Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? [Citation Graph (0, 0)][DBLP ] Conf ] 