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Publications of Author

1. María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas
   Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2003, pp:170-0 [Conf]
   
2. Enric Morancho, José María Llabería, Àngel Olivé
   Recovery Mechanism for Latency Misprediction. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2001, pp:118-0 [Conf]
   
3. Enric Morancho, José María Llabería, Àngel Olivé
   A Mechanism for Verifying Data Speculation. [Citation Graph (0, 0)][DBLP]
   Euro-Par, 2004, pp:525-534 [Conf]
   
4. Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería
   Counteracting Bank Misprediction in Sliced First-Level Caches. [Citation Graph (0, 0)][DBLP]
   Euro-Par, 2003, pp:586-596 [Conf]
   
5. Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería
   Contents Management in First-Level Multibanked Data Caches. [Citation Graph (0, 0)][DBLP]
   Euro-Par, 2004, pp:516-524 [Conf]
   
6. María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
   Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. [Citation Graph (0, 0)][DBLP]
   HPCA, 2003, pp:191-202 [Conf]
   
7. Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería
   Store Buffer Design in First-Level Multibanked Data Caches. [Citation Graph (0, 0)][DBLP]
   ISCA, 2005, pp:469-480 [Conf]
   
8. Enric Morancho, José María Llabería, Àngel Olivé
   A comparison of two policies for issuing instructions speculatively. [Citation Graph (0, 0)][DBLP]
   Journal of Systems Architecture, 2007, v:53, n:4, pp:170-183 [Journal]
   
9. Mateo Valero, Tomás Lang, José María Llabería, Montse Peiron, Juan J. Navarro, Eduard Ayguadé
   Conflict-Free Strides for Vectors in Matched Memories. [Citation Graph (0, 0)][DBLP]
   Parallel Processing Letters, 1991, v:1, n:, pp:95-102 [Journal]
   
10. María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
    Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:3, pp:247-279 [Journal]
    
11. 
    A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors. [Citation Graph (, )][DBLP]
    
    
12. 
    An Enhancement for a Scheduling Logic Pipelined over two Cycles . [Citation Graph (, )][DBLP]
    
    
13. 
    On reducing misspeculations in a pipelined scheduler. [Citation Graph (, )][DBLP]
    
    
14. 
    On reducing energy-consumption by late-inserting instructions into the issue queue. [Citation Graph (, )][DBLP]
    
    
15. 
    A performance evaluation of the multiple bus network for multiprocessor systems. [Citation Graph (, )][DBLP]