Conferences in DBLP

International Conference on Parallel Architectures and Compilation Techniques (PACT) (IEEEpact)
2001 (conf/IEEEpact/2001)

1. Timothy Sherwood, Erez Perelman, Brad Calder
   Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2001, pp:3-14 [Conf]
   
2. Sébastien Nussbaum, James E. Smith
   Modeling Superscalar Processors via Statistical Simulation. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2001, pp:15-24 [Conf]
   
3. Lieven Eeckhout, Koenraad De Bosschere
   Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2001, pp:25-0 [Conf]
   
4. Roni Rosner, Avi Mendelson, Ronny Ronen
   Filtering Techniques to Improve Trace-Cache Efficiency. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2001, pp:37-48 [Conf]
   
5. Brannon Batson, T. N. Vijaykumar
   Reactive-Associative Caches. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2001, pp:49-60 [Conf]
   
6. Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
   Adaptive Mode Control: A Static-Power-Efficient Cache Design. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2001, pp:61-0 [Conf]
   
7. Ben H. H. Juurlink, Stamatis Vassiliadis, Dmitri Tcheressiz, Harry A. G. Wijshoff
   Implementation and Evaluation of the Complex Streamed Instruction Set. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2001, pp:73-82 [Conf]
   
8. Jesús Corbal, Roger Espasa, Mateo Valero
   On the Efficiency of Reductions in µ-SIMD Media Extensions. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2001, pp:83-0 [Conf]
   
9. Daniel A. Jiménez, Heather L. Hanson, Calvin Lin
   Boolean Formula-Based Branch Prediction for Future Technologies. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2001, pp:97-106 [Conf]
   
10. Renju Thomas, Manoj Franklin
    Using Dataflow Based Context for Accurate Value Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:107-117 [Conf]
    
11. Enric Morancho, José María Llabería, Àngel Olivé
    Recovery Mechanism for Latency Misprediction. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:118-0 [Conf]
    
12. Bharat Chandramouli, John B. Carter, Wilson C. Hsieh, Sally A. McKee
    A Cost Framework for Evaluating Integrated Restructuring Optimizations. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:131-140 [Conf]
    
13. Xianglong Huang, Zhenlin Wang, Kathryn S. McKinley
    Compiling for the Impulse Memory Controller. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:141-150 [Conf]
    
14. Trishul M. Chilimbi
    On the Stability of Temporal Data Reference Profiles. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:151-0 [Conf]
    
15. Erik M. Nystrom, Ronald D. Barnes, Matthew C. Merten, Wen-mei W. Hwu
    Code Reordering and Speculation Support for Dynamic Optimization System. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:163-174 [Conf]
    
16. Josep M. Codina, F. Jesús Sánchez, Antonio González
    A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:175-184 [Conf]
    
17. Michael Penner, Viktor K. Prasanna
    Cache-Friendly Implementations of Transitive Closure. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:185-0 [Conf]
    
18. Jaehyuk Huh, Doug Burger, Stephen W. Keckler
    Exploring the Design Space of Future CMPs. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:199-210 [Conf]
    
19. James Burns, Jean-Luc Gaudiot
    Area and System Clock Effects on SMT/CMP Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:211-0 [Conf]
    
20. Fredrik Warg, Per Stenström
    Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:221-230 [Conf]
    
21. Renato Ferreira, Joel H. Saltz, Gagan Agrawal
    Compiler and Runtime Analysis for Efficient Communication in Data Intensive Applications. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:231-242 [Conf]
    
22. María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Josep Torrellas, Alin Jula, Hao Yu, Lawrence Rauchwerger
    Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:243-0 [Conf]
    
23. Gautam Doshi, Rakesh Krishnaiyer, Kalyan Muthukumar
    Optimizing Software Data Prefetches with Rotating Registers. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:257-267 [Conf]
    
24. Nicholas Kohout, Seungryul Choi, Dongkeun Kim, Donald Yeung
    Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:268-279 [Conf]
    
25. Brendon Cahoon, Kathryn S. McKinley
    Data Flow Analysis for Software Prefetching Linked Data Structures in Java. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:280-291 [Conf]
    
26. Vijay S. Pai, Sarita V. Adve
    Comparing and Combining Read Miss Clustering and Software Prefetching. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:292-0 [Conf]