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Conferences in DBLP

International Symposium on High-Performance Computer Architecture (HPCA) (hpca)
2003 (conf/hpca/2003)

  1. Dileep Bhandarkar
    Billion Transistor Chips in Mainstream Enterprise Platforms of the Future. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:3-0 [Conf]
  2. Alaa R. Alameldeen, David A. Wood
    Variability in Architectural Simulations of Multi-Threaded Workloads. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:7-18 [Conf]
  3. Joshua Redstone, Susan J. Eggers, Henry M. Levy
    Mini-Threads: Increasing TLP on Small-Scale SMT Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:19-30 [Conf]
  4. Ali El-Moursy, David H. Albonesi
    Front-End Policies for Improved Issue Efficiency in SMT Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:31-0 [Conf]
  5. Daniel A. Jiménez
    Reconsidering Complex Branch Predictors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:43-52 [Conf]
  6. Beth Simon, Brad Calder, Jeanne Ferrante
    Incorporating Predicate Information into Branch Predictors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:53-64 [Conf]
  7. Lei Chen, Steve Dropsho, David H. Albonesi
    Dynamic Data Dependence Tracking and its Application to Branch Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:65-0 [Conf]
  8. Russ Joseph, David Brooks, Margaret Martonosi
    Control Techniques to Eliminate Voltage Emergencies in High Performance Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:79-90 [Conf]
  9. Li Shang, Li-Shiuan Peh, Niraj K. Jha
    Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:91-102 [Conf]
  10. Juan L. Aragón, José González, Antonio González
    Power-Aware Control Speculation through Selective Throttling. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:103-112 [Conf]
  11. Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy
    Deterministic Clock Gating for Microprocessor Power Reduction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:113-0 [Conf]
  12. Eric Kronstadt
    Beyond Performance: Some (Other) Challenges for Systems Design. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:125-0 [Conf]
  13. Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt
    Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:129-140 [Conf]
  14. Mariko Sakamoto, Akira Katsuno, Aiichiro Inoue, Takeo Asakawa, Haruhiko Ueno, Kuniki Morita, Yasunori Kimura
    Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:141-152 [Conf]
  15. Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles
    Exploring the VLSI Scalability of Stream Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:153-164 [Conf]
  16. Brian Slechta, David Crowe, Brian Fahs, Michael Fertig, Gregory A. Muthler, Justin Quek, Francesco Spadini, Sanjay J. Patel, Steven Lumetta
    Dynamic Optimization of Micro-Operations. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:165-0 [Conf]
  17. Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg
    Slipstream Execution Mode for CMP-Based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:179-190 [Conf]
  18. María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
    Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:191-202 [Conf]
  19. Rosalia Christodoulopoulou, Reza Azimi, Angelos Bilas
    Dynamic Data Replication: An Approach to Providing Fault-Tolerant Shared Memory Clusters. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:203-0 [Conf]
  20. Martin Karlsson, Kevin E. Moore, Erik Hagersten, David A. Wood
    Memory System Behavior of Java-Based Middleware. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:217-228 [Conf]
  21. Kiran Nagaraja, Neeraj Krishnan, Ricardo Bianchini, Richard P. Martin, Thu D. Nguyen
    Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:229-240 [Conf]
  22. Zoran Radovic, Erik Hagersten
    Hierarchical Backoff Locks for Nonuniform Communication Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:241-252 [Conf]
  23. Eun Jung Kim, Ki Hwan Yum, Chita R. Das, Mazin S. Yousif, José Duato
    Performance Enhancement Techniques for InfiniBand? Architecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:253-0 [Conf]
  24. Peter M. Kogge
    The State of State. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:266-0 [Conf]
  25. Satish Narayanasamy, Timothy Sherwood, Suleyman Sair, Brad Calder, George Varghese
    Catching Accurate Profiles in Hardwar. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:269-280 [Conf]
  26. Joshua J. Yi, David J. Lilja, Douglas M. Hawkins
    A Statistically Rigorous Approach for Improving Simulation Methodology. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:281-0 [Conf]
  27. Blaise Gassend, G. Edward Suh, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas
    Caches and Hash Trees for Efficient Memory Integrity. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:295-306 [Conf]
  28. Gokhan Memik, Glenn Reinman, William H. Mangione-Smith
    Just Say No: Benefits of Early Cache Miss Determinatio. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:307-316 [Conf]
  29. Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
    TCP: Tag Correlating Prefetchers. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:317-326 [Conf]
  30. Jaeheon Jeong, Michel Dubois
    Cost-Sensitive Cache Replacement Algorithms. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:327-0 [Conf]
  31. Michael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal
    Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:341-353 [Conf]
  32. Andrei Terechko, Erwan Le Thenaff, Manish Garg, Jos T. J. van Eijndhoven, Henk Corporaal
    Inter-Cluster Communication Models for Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:354-364 [Conf]
  33. Ming Hao, Mark Heinrich
    Active I/O Switches in System Area Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:365-376 [Conf]
  34. Wai Hong Ho, Timothy Mark Pinkston
    A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:377-0 [Conf]
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