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Mrinmoy Ghosh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu
    Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:123-134 [Conf]
  2. Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien-Hsin S. Lee
    Efficient System-on-Chip Energy Management with a Segmented Bloom Filter. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:283-297 [Conf]
  3. Dong Hyuk Woo, Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien-Hsin S. Lee
    Reducing energy of virtual cache synonym lookup using bloom filters. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:179-189 [Conf]
  4. Weidong Shi, Hsien-Hsin S. Lee, Guofei Gu, Laura Falk, Trevor N. Mudge, Mrinmoy Ghosh
    An Intrusion-Tolerant and Self-Recoverable Network Service System Using A Security Enhanced Chip Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICAC, 2005, pp:263-273 [Conf]
  5. Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmoy Ghosh
    An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:102-113 [Conf]
  6. Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu, Alexandra Boldyreva
    High Efficiency Counter Mode Security Architecture via Prediction and Precomputation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:14-24 [Conf]
  7. Weidong Shi, Hsien-Hsin S. Lee, Chenghuai Lu, Mrinmoy Ghosh
    Towards the issues in architectural support for protection of software execution. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:1, pp:6-15 [Journal]
  8. Rajeev Kumar, Amit Gupta, B. S. Pankaj, Mrinmoy Ghosh, P. P. Chakrabarti
    Post-compilation optimization for multiple gains with pattern matching. [Citation Graph (0, 0)][DBLP]
    SIGPLAN Notices, 2005, v:40, n:12, pp:14-23 [Journal]

  9. Virtual Exclusion: An architectural approach to reducing leakage energy in caches for multiprocessor systems. [Citation Graph (, )][DBLP]


  10. Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches. [Citation Graph (, )][DBLP]


  11. Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. [Citation Graph (, )][DBLP]


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