Journals in DBLP

Microelectronics Reliability
2004, volume: 44, number: 5

1. B. L. Yang, P. T. Lai, H. Wong
   Conduction mechanisms in MOS gate dielectric films. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2004, v:44, n:5, pp:709-718 [Journal]
   
2. Paul S. Ho, Guotao Wang, Min Ding, Jie-Hua Zhao, Xiang Dai
   Reliability issues for flip-chip packages. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2004, v:44, n:5, pp:719-737 [Journal]
   
3. Domenico Caputo, Fernanda Irrera
   On the reliability of ZrO₂ films for VLSI applications. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2004, v:44, n:5, pp:739-745 [Journal]
   
4. A. V. Vairagar, S. G. Mhaisalkar, Ahila Krishnamoorthy
   Electromigration behavior of dual-damascene Cu interconnects--Structure, width, and length dependences. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2004, v:44, n:5, pp:747-754 [Journal]
   
5. Peter Z. F. Shi, Albert C. W. Lu, Y. M. Tan, Stephen C. K. Wong, Eric Tan, Ronson Tan
   Thermal design and experimental validation for optical transmitters. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2004, v:44, n:5, pp:755-769 [Journal]
   
6. Yoshiteru Yamada, Hirotaka Komoda
   An example of fault site localization on a 0.18 mum CMOS device with combination of front and backside techniques. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2004, v:44, n:5, pp:771-778 [Journal]
   
7. Zhimin Mo, Helge Kristiansen, Morten Eliassen, Shiming Li, Johan Liu
   Study on thermomechanical reliability of a tunable light modulator. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2004, v:44, n:5, pp:779-785 [Journal]
   
8. Mark A. Fritz, Daniel T. Cassidy
   Extraction of bonding strain data in diode lasers from polarization-resolved photoluminescence measurements. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2004, v:44, n:5, pp:787-796 [Journal]
   
9. Dionysios Manessis, Rainer Patzelt, Andreas Ostmann, Rolf Aschenbrenner, Herbert Reichl
   Technical challenges of stencil printing technology for ultra fine pitch flip chip bumping. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2004, v:44, n:5, pp:797-803 [Journal]
   
10. Frank Stepniak
    Mechanical loading of flip chip joints before underfill: the impact on yield and reliability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:5, pp:805-814 [Journal]
    
11. Rashed Adnan Islam, Y. C. Chan
    Effect of microwave preheating on the bonding performance of flip chip on flex joint. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:5, pp:815-821 [Journal]
    
12. C. W. Tan, Y. C. Chan, H. P. Chan, N. W. Leung, C. K. So
    Investigation on bondability and reliability of UV-curable adhesive joints for stable mechanical properties in photonic device packaging. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:5, pp:823-831 [Journal]
    
13. Jinlin Wang, H. K. Lim, H. S. Lew, Woon Theng Saw, Chew Hong Tan
    A testing method for assessing solder joint reliability of FCBGA packages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:5, pp:833-840 [Journal]
    
14. X. Q. Shi, H. L. J. Pang, X. R. Zhang
    Investigation of long-term reliability and failure mechanism of solder interconnections with multifunctional micro-moiré interferometry system. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:5, pp:841-852 [Journal]
    
15. L. Han, A. Voloshin
    Statistical analysis for test lands positioning and PCB deformation during electrical testing. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:5, pp:853-859 [Journal]
    
16. Pawel Sniatala, André S. Botha
    A/D converter based on a new memory cell implemented using the switched current technique. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:5, pp:861-867 [Journal]
    
17. Aránzazu Otín, Santiago Celma, Concepción Aldea
    Digitally programmable CMOS transconductor for very high frequency. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:5, pp:869-875 [Journal]
    
18. O. Mitrea, Manfred Glesner
    A power-constrained design strategy for CMOS tuned low noise amplifiers. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:5, pp:877-883 [Journal]
    
19. V. Sánchez, J. Munguía, M. Estrada
    Photo-CVD process for ultra thin SiO₂ films. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:5, pp:885-888 [Journal]