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Manfred Glesner: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Heiko Hinkelmann, Peter Zipf, Manfred Glesner
    A metric for the energy-efficiency of dynamically reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:152-161 [Conf]
  2. Heiko Hinkelmann, Thilo Pionteck, Oliver Kleine, Manfred Glesner
    Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:45-51 [Conf]
  3. Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Lukusa D. Kabulepa, Manfred Glesner
    Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:155-164 [Conf]
  4. Marc Theisen, Jürgen Becker, Manfred Glesner, Tri Caohuu
    Parallel Hardware Compilation in Complex Hardware/Software Systems based on High-Level Code Transformations. [Citation Graph (0, 0)][DBLP]
    ARCS, 1999, pp:143-154 [Conf]
  5. Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, A. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, A. Rubio
    CONAN - A Design Exploration Framework for Reliable Nano-Electronics. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:260-267 [Conf]
  6. Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner
    Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:404-418 [Conf]
  7. Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan
    Reconfigurable platforms for ubiquitous computing. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:377-389 [Conf]
  8. Thomas Hollstein, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner
    HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:29-33 [Conf]
  9. Manfred Glesner, Johannes Schuck, R. B. Steck
    SCAT - a new statistical timing verifier in a silicon compiler system. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:220-226 [Conf]
  10. Jean-Michel Karam, Bernard Courtois, Hicham Boutamine, P. Drake, A. Poppe, Vladimir Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner
    CAD and Foundries for Microsystems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:674-679 [Conf]
  11. Jochen Mades, Manfred Glesner
    Regularization of hierarchical VHDL-AMS models using bipartite graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:548-551 [Conf]
  12. Sujan Pandey, Manfred Glesner
    Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:663-668 [Conf]
  13. Johannes Schuck, Norbert Wehn, Manfred Glesner, G. Kamp
    The ALGIC Silicon Compiler System: Implementation, Design Experience and Results. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:370-375 [Conf]
  14. Norbert Wehn, Manfred Glesner, K. Caesar, P. Mann, A. Roth
    A Defect-Tolerant and Fully Testable PLA. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:22-33 [Conf]
  15. Michael Gasteier, Manfred Glesner, Michael Münch
    Generation of Interconnect Topologies for Communication Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:36-0 [Conf]
  16. Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis
    Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1130- [Conf]
  17. Leandro Soares Indrusiak, Florian Lubitz, Ricardo Augusto da Luz Reis, Manfred Glesner
    Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10940-10945 [Conf]
  18. Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
    Estimation of Power Consumption in Encoded Data Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1103- [Conf]
  19. Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred Glesner
    A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:632-637 [Conf]
  20. Peter Gerken, Stefan Schultz, Gerald Knabe, Franco Casalino, Gianluca Di Cagno, Mauro Quaglia, Jean-Claude Dufourd, Souhila Boughoufalah, Frédéric Bouilhaguet, Michael Stepping, Thomas Bonse, Ulrich Mayer, Jürgen Deicke, Manfred Glesner
    MPEG-4 PC - Authoring and Playing of MPEG-4 Content for Local and Broadcast Applications. [Citation Graph (0, 0)][DBLP]
    ECMAST, 1999, pp:108-119 [Conf]
  21. Manfred Glesner, Matthias Rychetsky, Stefan Ortmann
    Advanced Hardware and Software Architectures for Computational Intelligence: Application to a Real World Problem. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:21068-0 [Conf]
  22. Ahmad Alsolaim, Janusz A. Starzyk, Jürgen Becker, Manfred Glesner
    Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:205-216 [Conf]
  23. Stephan Bingemer, Peter Zipf, Manfred Glesner
    A granularity-based classification model for systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:239- [Conf]
  24. Peter Poechmueller, Hans-Jürgen Herpel, Manfred Glesner, Fang Longsen
    High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:96-105 [Conf]
  25. Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
    On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:258- [Conf]
  26. Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner
    Perspectives of Reconfigurable Computing in Research, Industry and Education. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:39-48 [Conf]
  27. Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner
    Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:584-589 [Conf]
  28. Jürgen Becker, Thilo Pionteck, Manfred Glesner
    DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:312-321 [Conf]
  29. Tri Caohuu, Thuy Trong Le, Manfred Glesner, Jürgen Becker
    Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:507-513 [Conf]
  30. Hans-Jürgen Herpel, Ulrike Ober, Manfred Glesner
    Prototype Generation of Application-Specific Embedded Controllers for Microsystems. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:341-351 [Conf]
  31. Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner
    Fly - A Modifiable Hardware Compiler. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:381-390 [Conf]
  32. Thomas Hollstein, Andreas Kirschbaum, Manfred Glesner
    A prototyping environment for fuzzy controllers. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:482-490 [Conf]
  33. Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong
    IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:526-535 [Conf]
  34. Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek
    Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1111-1114 [Conf]
  35. Ulrike Ober, Hans-Jürgen Herpel, Manfred Glesner
    CAPpartx: Computer Aided Prototyping Partitioning for Xilinx FPGAs, a Hierarchical Partitioning Tool for Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:106-115 [Conf]
  36. Sujan Pandey, Manfred Glesner, Max Mühlhäuser
    On-Chip Communication Topology Synthesis for a Shared Memory Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:374-379 [Conf]
  37. Mihail Petrov, Tudor Murgan, F. May, Martin Vorbach, Peter Zipf, Manfred Glesner
    The XPP Architecture and Its Co-simulation Within the Simulink Environment. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:761-770 [Conf]
  38. Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
    A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1090-1092 [Conf]
  39. Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner
    A Framework for Teaching (Re)Configurable Architectures in Student Projects. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:444-451 [Conf]
  40. Frank-Michael Renner, Jürgen Becker, Manfred Glesner
    Field Programmable Communication Emulation and Optimization for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:58-67 [Conf]
  41. Frank-Michael Renner, Jürgen Becker, Manfred Glesner
    An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:179-188 [Conf]
  42. U. Zahm, Thomas Hollstein, Hans-Jürgen Herpel, Norbert Wehn, Manfred Glesner
    Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:241-250 [Conf]
  43. Peter Zipf, Manfred Glesner, Christine Bauer, Hans Wojtkowiak
    Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:586-595 [Conf]
  44. Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner
    Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:329-334 [Conf]
  45. Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner
    A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:335-340 [Conf]
  46. Mihail Petrov, Manfred Glesner
    Optimal FFT Architecture Selection for OFDM Receivers on FPGA. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:313-314 [Conf]
  47. Mihail Petrov, Manfred Glesner
    A State-Serial Viterbi Decoder Architecture for Digital Radio on FPGA. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:323-324 [Conf]
  48. Thomas Hollstein, Saman K. Halgamuge, Andreas Kirschbaum, Manfred Glesner
    Rapid-Prototyping von anwendungsspezifischen Fuzzy Controllern mit Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    Fuzzy Days, 1994, pp:8-14 [Conf]
  49. Manfred Glesner, M. Huch, Peter A. Ivey, T. Midwinter, Gabriele Saucier, Jacques Trilhe
    Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 1988, pp:75-91 [Conf]
  50. Clemens Schlachta, Oliver Soffke, Peter Zipf, Manfred Glesner
    Eine weiterentwickelte quasi-statische adiabatische Logikfamilie. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:448- [Conf]
  51. Peter Zipf, Oliver Soffke, Michael Velten, Manfred Glesner
    Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:329-333 [Conf]
  52. Hans-Jürgen Herpel, Michael Held, Manfred Glesner
    A Design Methodology for the Conceptual Design of Application Specific Digital Processors in Mechatronic Systems. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:78-86 [Conf]
  53. Alberto García Ortiz, Lukusa D. Kabulepa, Tudor Murgan, Manfred Glesner
    Moment-Based Power Estimation in Very Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:107-112 [Conf]
  54. Martin K. F. Schafer, Thomas Hollstein, Heiko Zimmer, Manfred Glesner
    Deadlock-free routing and component placement for irregular mesh-based networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:238-245 [Conf]
  55. Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner
    A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:323-328 [Conf]
  56. Peter Poechmueller, Manfred Glesner
    A New Approach for Designing Fault-Tolerant Array Processors. [Citation Graph (0, 0)][DBLP]
    Fault-Tolerant Computing Systems, 1991, pp:324-331 [Conf]
  57. Matthias Rychetsky, John Shawe-Taylor, Manfred Glesner
    Direct Bayes Point Machines. [Citation Graph (0, 0)][DBLP]
    ICML, 2000, pp:815-822 [Conf]
  58. Jürgen Deicke, Ulrich Mayer, Manfred Glesner
    An Object-Oriented Client/Server Architecture for Video-on-Demand Applications. [Citation Graph (0, 0)][DBLP]
    IDMS, 1997, pp:440-449 [Conf]
  59. Jürgen Deicke, Ulrich Mayer, A. Knoll, Manfred Glesner
    Flexible Multiplexing in MPEG-4 Systems. [Citation Graph (0, 0)][DBLP]
    IDMS, 1998, pp:83-94 [Conf]
  60. Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis
    Distributed Collaborative Design over Cave2 Framework. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:97-108 [Conf]
  61. Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
    ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:659-670 [Conf]
  62. Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
    A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:61-66 [Conf]
  63. Heiko Zimmer, Stefan Zink, Thomas Hollstein, Manfred Glesner
    Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  64. Radu Dogaru, Ioana Dogaru, Manfred Glesner
    Compact image compression using simplicial and ART neural systems with mixed signal implementations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:689-692 [Conf]
  65. Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner
    A linear model for high-level delay estimation in VDSM on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1078-1081 [Conf]
  66. Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser
    High level hardware/software communication estimation in shared memory architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:37-40 [Conf]
  67. B. Voss, Manfred Glesner
    A low power sinusoidal clock. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:108-111 [Conf]
  68. Mihail Petrov, Tudor Murgan, Abdulfattah Mohammad Obeid, Cristian Chitu, Peter Zipf, Jörg Brakensiek, Manfred Glesner
    Dynamic power optimization of the trace-back process for the Viterbi algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:721-724 [Conf]
  69. Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
    Design of a reconfigurable AES encryption/decryption engine for mobile terminals. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:545-548 [Conf]
  70. Lukusa D. Kabulepa, Alberto García Ortiz, Manfred Glesner
    Power reduction techniques for an OFDM burst synchronization core. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:265-268 [Conf]
  71. Lukusa D. Kabulepa, Alberto García Ortiz, Manfred Glesner
    Design of an efficient OFDM burst synchronization scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:449-452 [Conf]
  72. Jochen Mades, D. E. Schwarz, Manfred Glesner
    A discrete algorithm for the regularization of hierarchical VHDL-AMS models. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:477-480 [Conf]
  73. Ulrich Mayer, Jürgen Deicke, Manfred Glesner
    Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams Connected to (R)CBR Channels. [Citation Graph (0, 0)][DBLP]
    ISCC, 2000, pp:298-303 [Conf]
  74. Alberto García, Lukusa D. Kabulepa, Manfred Glesner
    Efficient estimation of signal transition activity in MAC architectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:319-322 [Conf]
  75. Michael Gasteier, Manfred Glesner
    Bus-Based Communication Synthesis on System-Level. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:65-70 [Conf]
  76. Michael Münch, Manfred Glesner, Norbert Wehn
    An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:45-50 [Conf]
  77. Peter Zipf, Claude Stötzler, Manfred Glesner
    A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:266-267 [Conf]
  78. José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes
    Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:426-427 [Conf]
  79. Romualdo Begale Prudencio, Leandro Soares Indrusiak, Manfred Glesner
    An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS Standard. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:77-84 [Conf]
  80. José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
    Inserting Data Encoding Techniques into NoC-Based Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:299-304 [Conf]
  81. Hans-Jürgen Herpel, Michael Held, Manfred Glesner
    MCEMS Toolbox - A Hardware-in-the-Loop Simulation Environment for Mechatronic Systems. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 1994, pp:356-357 [Conf]
  82. Norbert Wehn, Manfred Glesner, A. Kister, S. Kastner
    Timing Driven Partitioning of Combinational Logic. [Citation Graph (0, 0)][DBLP]
    Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1990, pp:42-51 [Conf]
  83. Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis, Giuliana Alcántara, Stefan Hoermann, Ralf Steinmetz
    Reducing Authoring Costs of Online Training in Microelectronics Design by Reusing Design Documentation Content. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:57-58 [Conf]
  84. Jochen Mades, T. Schneider, A. Windisch, Thomas Hollstein, Jürgen Becker, Manfred Glesner
    Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:2-3 [Conf]
  85. Diego Fernando Jimenez Orostegui, Leandro Soares Indrusiak, Manfred Glesner
    Proxy-Based Integration of Reconfigurable Hardware Within Simulation Environments: Improving E-Learning Experience in Microelectronics. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:59-60 [Conf]
  86. Stefan Ortmann, Matthias Rychetsky, Manfred Glesner
    Constructive Learning of a Sub-Feature Detector Network by Means of Prediction Risk Estimation. [Citation Graph (0, 0)][DBLP]
    NC, 1998, pp:995-1001 [Conf]
  87. Matthias Rychetsky, Stefan Ortmann, Manfred Glesner
    Pruning and Regularization Techniques for Feed Forward Nets Applied on a Real World Data Base. [Citation Graph (0, 0)][DBLP]
    NC, 1998, pp:603-609 [Conf]
  88. Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
    Switching Activity Estimation in Non-linear Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:269-278 [Conf]
  89. Tudor Murgan, P. B. Bacinschi, Alberto García Ortiz, Manfred Glesner
    Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:169-180 [Conf]
  90. Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner
    On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:819-828 [Conf]
  91. Alberto García Ortiz, Tudor Murgan, Manfred Glesner
    Moment-Based Estimation of Switching Activity for Correlated Distributions. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:859-868 [Conf]
  92. José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
    Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:603-613 [Conf]
  93. Clemens Schlachta, Manfred Glesner
    A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:563-572 [Conf]
  94. Jürgen Becker, Manfred Glesner
    IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  95. Jürgen Becker, Manfred Glesner, Ahmad Alsolaim, Janusz A. Starzyk
    Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  96. Kurt Franz Ackermann, Friedhelm Mayer, Leandro Soares Indrusiak, Manfred Glesner
    Adaptable Image Processing System based on FPGA Modular Multi Kernel Instantiations. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:183-188 [Conf]
  97. Hua Zhong, Leandro Soares Indrusiak, Heiko Hinkelmann, Manfred Glesner
    Exploring Functional Unit Parallelism in Reconfigurable Computing Platforms. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:160-167 [Conf]
  98. Peter Zipf, Claude Stötzler, Manfred Glesner
    Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:53-58 [Conf]
  99. Heiko Hinkelmann, Peter Zipf, Manfred Glesner
    A Concept for a Profile-based Dynamic Reconfiguration Mechanism. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:105-110 [Conf]
  100. Thomas Hollstein, Sujan Pandey, Manfred Glesner
    Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:85-92 [Conf]
  101. Leandro Soares Indrusiak, Manfred Glesner
    Experiences on Actor-oriented Design of Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:79-84 [Conf]
  102. Tudor Murgan, Abdulfattah Mohammad Obeid, Andre Guntoro, Peter Zipf, Manfred Glesner, Ulrich Heinkel
    Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:151-156 [Conf]
  103. Chun Hok Ho, M. P. Leong, Philip Heng Wai Leong, Jürgen Becker, Manfred Glesner
    Rapid Prototyping of FPGA Based Floating Point DSP Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:19-24 [Conf]
  104. Jürgen Becker, Lukusa D. Kabulepa, Frank-Michael Renner, Manfred Glesner
    Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:160-0 [Conf]
  105. Leandro Soares Indrusiak, Romualdo Begale Prudencio, Manfred Glesner
    Modeling and Prototyping of Communication Systems Using Java: A Case Study. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:225-231 [Conf]
  106. Abdulfattah Mohammad Obeid, Alberto García Ortiz, Ralf Ludewig, Manfred Glesner
    Prototyping of a High Performance Generic Viterbi Decoder. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:42-47 [Conf]
  107. Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
    Run-Time Monitoring of Communication Activities in a Rapid Prototyping Environment. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:52-57 [Conf]
  108. Amar Mukherjee, Nitin Motgi, Jürgen Becker, A. Friebe, C. Habermann, Manfred Glesner
    Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2001, pp:58-63 [Conf]
  109. Andreas Kirschbaum, Stefan Ortmann, Manfred Glesner
    Rapid Prototyping of a Co-Processor Based Engine Knock Detection System. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:124-129 [Conf]
  110. Thilo Pionteck, A. Garcya, Lukusa D. Kabulepa, Manfred Glesner
    The requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:141-147 [Conf]
  111. Thilo Pionteck, N. Toender, Lukusa D. Kabulepa, Manfred Glesner, T. Kella
    On the Rapid Prototyping of Equalizers for OFDM Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:48-52 [Conf]
  112. Frank-Michael Renner, Jürgen Becker, Manfred Glesner
    Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:154-159 [Conf]
  113. Frank-Michael Renner, Jürgen Becker, Manfred Glesner
    Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:108-113 [Conf]
  114. Ralf Ludewig, Thomas Hollstein, Falko Schütz, Manfred Glesner
    Rapid Prototyping of an Integrated Testing and Debugging Unit. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:187-192 [Conf]
  115. Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Manfred Glesner
    Power Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:138-0 [Conf]
  116. Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Juan Jesus, Ocampo Hidalgo, Manfred Glesner
    Emulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:172-178 [Conf]
  117. Ulrich Mayer, Manfred Glesner
    Hardware Accelerated Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:214-0 [Conf]
  118. H. Genther, Manfred Glesner
    Automatic generation of a fuzzy classification system using fuzzy clustering methods. [Citation Graph (0, 0)][DBLP]
    SAC, 1994, pp:180-183 [Conf]
  119. Saman K. Halgamuge, Alain Brichard, Manfred Glesner
    Comparison of a heuristic method with a genetic algorithm for generation of compact rule based classifiers. [Citation Graph (0, 0)][DBLP]
    SAC, 1995, pp:580-585 [Conf]
  120. Saman K. Halgamuge, Manfred Glesner
    Fuzzy neural fusion techniques for industrial applications. [Citation Graph (0, 0)][DBLP]
    SAC, 1994, pp:136-141 [Conf]
  121. Saman K. Halgamuge, Christoph Grimm, Manfred Glesner
    A sub Bayesian nearest prototype neural network with fuzzy interpretability for diagnosis problems. [Citation Graph (0, 0)][DBLP]
    SAC, 1995, pp:445-449 [Conf]
  122. Thomas A. Runkler, Manfred Glesner
    DECADE - fast centroid approximation defuzzification for real time fuzzy control applications. [Citation Graph (0, 0)][DBLP]
    SAC, 1994, pp:161-165 [Conf]
  123. Thomas A. Runkler, Manfred Glesner
    Multidimensional defuzzification - fast algorithms for the determination of crisp characteristic subsets. [Citation Graph (0, 0)][DBLP]
    SAC, 1995, pp:575-579 [Conf]
  124. Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf
    Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:12-21 [Conf]
  125. Elvio Dutra, Leandro Soares Indrusiak, Manfred Glesner
    Non-linear addressing scheme for a lookup-based transformation function in a reconfigurable noise generator. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:242-247 [Conf]
  126. Sujan Pandey, Manfred Glesner, Max Mühlhäuser
    Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:230-235 [Conf]
  127. Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner
    A switch architecture and signal synchronization for GALS system-on-chips. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:210-215 [Conf]
  128. Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
    Accurate capture of timing parameters in inductively-coupled on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:117-122 [Conf]
  129. Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis
    Lookup-based Remote Laboratory for FPGA Digital Design Prototyping. [Citation Graph (0, 0)][DBLP]
    VIRTUAL-LAB, 2004, pp:3-11 [Conf]
  130. Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner
    A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:44-49 [Conf]
  131. Stephan Bingemer, Peter Zipf, Manfred Glesner
    An Integrated Model Bridging the Gap between Technology and Economy. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:442-0 [Conf]
  132. Cristian Chitu, Manfred Glesner
    High Performance of an AES-Rijndael ASIC working in OCB/ECB Modes of Operation. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:62-67 [Conf]
  133. A. Laudenbach, Manfred Glesner, Norbert Wehn
    A VLSI System Design for the Control of High Performance Combustion Engines. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:247-256 [Conf]
  134. Radu Dogaru, Cristian Chitu, Manfred Glesner
    A Versatile Cellular Neural Circuit Based on a Multi-nested Approach: Functional Capabilities and Applications. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:356-361 [Conf]
  135. Norbert Wehn, Manfred Glesner, C. Vielhauer
    Estimating lower hardware bounds in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI, 1993, pp:261-270 [Conf]
  136. Mihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner
    An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:167-0 [Conf]
  137. Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner
    Exploring the Capabilities of Reconfigurable Hardware for OFDM-based WLANs. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:161-166 [Conf]
  138. Bernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimir Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner
    Design and Test of MEMs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:270-0 [Conf]
  139. Alberto García Ortiz, Tudor Murgan, Manfred Glesner
    Transition Activity Estimation for General Correlated Data Distributions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:440-445 [Conf]
  140. Heiko Hinkelmann, Peter Zipf, Manfred Glesner
    Design Concepts for a Dynamically ReconfigurableWireless Sensor Node. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:436-441 [Conf]
  141. Jürgen Deicke, Ulrich Mayer, Manfred Glesner
    A client/server application as an example for MPEG-4 systems. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1998, v:21, n:15, pp:1302-1309 [Journal]
  142. Saman K. Halgamuge, Werner Poechmueller, Manfred Glesner
    An alternative approach for generation of membership functions and fuzzy rules based on radial and cubic basis function networks. [Citation Graph (0, 0)][DBLP]
    Int. J. Approx. Reasoning, 1995, v:12, n:3-4, pp:279-298 [Journal]
  143. Saman K. Halgamuge, Manfred Glesner
    Fuzzy neural networks: between functional equivalence and applicability. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 1995, v:6, n:2, pp:185-196 [Journal]
  144. Werner Poechmueller, Manfred Glesner
    Evaluation of state-of-the-art neural network customized hardware. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 1990, v:2, n:5, pp:209-231 [Journal]
  145. Stefan Ortmann, Manfred Glesner
    Development and Implementation of a Neural Knock Detector Using Constructive Learning Methods. [Citation Graph (0, 0)][DBLP]
    International Journal of Uncertainty, Fuzziness and Knowledge-Based Systems, 1998, v:6, n:2, pp:127-138 [Journal]
  146. Alexander Steudel, Manfred Glesner
    Fuzzy segmented image coding using orthonormal bases and derivative chain coding. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1999, v:32, n:11, pp:1827-1841 [Journal]
  147. Leandro Soares Indrusiak, Ricardo A. L. Reis, Manfred Glesner
    Um Framework de Apoio à Colaboração no Projeto Distribuído de Sistemas Integrados. [Citation Graph (0, 0)][DBLP]
    RITA, 2004, v:11, n:2, pp:49-74 [Journal]
  148. Hans-Jürgen Herpel, Manfred Glesner
    Rapid Prototyping of Real-Time Information Processing Units for Mechatronic Systems. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 1998, v:14, n:3, pp:269-291 [Journal]
  149. Thuyen Le, Manfred Glesner
    Flexible architectures for DCT of variable-length targeting shape-adaptive transform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2000, v:10, n:8, pp:1489-1495 [Journal]
  150. Jürgen Becker, Manfred Glesner
    A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2001, v:19, n:1, pp:105-127 [Journal]
  151. Michael Gasteier, Manfred Glesner
    Bus-based communication synthesis on system level. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:1, pp:1-11 [Journal]
  152. Michael Münch, Norbert Wehn, Manfred Glesner
    An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:4, pp:344-364 [Journal]
  153. O. Mitrea, Manfred Glesner
    A power-constrained design strategy for CMOS tuned low noise amplifiers. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:5, pp:877-883 [Journal]
  154. Cristian Chitu, Manfred Glesner
    An FPGA implementation of the AES-Rijndael in OCB/ECB modes of operation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:2, pp:139-146 [Journal]
  155. Leandro Soares Indrusiak, Andreas Thuy, Manfred Glesner
    Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:301-306 [Conf]
  156. Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner
    Multitasking Support for Dynamically Reconfig Urable Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  157. Sujan Pandey, Manfred Glesner
    Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  158. Sujan Pandey, Manfred Glesner
    Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  159. Tudor Murgan, P. B. Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
    On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:242-254 [Conf]
  160. Heiko Hinkelmann, Tudor Murgan, G. Liu, Peter Zipf, Manfred Glesner
    On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:185-191 [Conf]
  161. Kurt Franz Ackermann, Leandro Soares Indrusiak, Manfred Glesner
    System Level Design of a Dynamically Self-Reconfigurable Image Processing System. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:47-54 [Conf]
  162. Tudor Murgan, Andre Guntoro, Heiko Hinkelmann, P. B. Bacinschi, Manfred Glesner
    Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:7-14 [Conf]
  163. Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner
    A Customizable LEON2-Based VLIW Processor. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:55-60 [Conf]
  164. Sujan Pandey, Nurten Utlu, Manfred Glesner
    Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:222-227 [Conf]
  165. Tudor Murgan, O. Mitrea, Sujan Pandey, P. B. Bacinschi, Manfred Glesner
    Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:302-307 [Conf]
  166. Sujan Pandey, Tudor Murgan, Manfred Glesner
    Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:296-301 [Conf]
  167. Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
    On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:283-297 [Conf]
  168. Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner
    Implementation of Realtime and Highspeed Phase Detector on FPGA. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:1-11 [Conf]
  169. Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck
    Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:3, pp:174-0 [Journal]
  170. Sujan Pandey, Manfred Glesner
    Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1111-1124 [Journal]
  171. Thomas Hollstein, Manfred Glesner
    Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2007, v:33, n:4, pp:310-319 [Journal]

  172. Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters. [Citation Graph (, )][DBLP]


  173. Towards an Automated Design of Application-specific Reconfigurable Logic. [Citation Graph (, )][DBLP]


  174. An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs. [Citation Graph (, )][DBLP]


  175. Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation. [Citation Graph (, )][DBLP]


  176. Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems. [Citation Graph (, )][DBLP]


  177. Multicast Parallel Pipeline Router Architecture for Network-on-Chip. [Citation Graph (, )][DBLP]


  178. Generation of the HDL-A-model of a micromembrane from its finite-element-description. [Citation Graph (, )][DBLP]


  179. A flexible floating-point wavelet transform and wavelet packet processor. [Citation Graph (, )][DBLP]


  180. Multiway netlist partitioning onto FPGA-based board architecture. [Citation Graph (, )][DBLP]


  181. Generating compilers for generated datapaths. [Citation Graph (, )][DBLP]


  182. Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations. [Citation Graph (, )][DBLP]


  183. A Power Estimation Model for an FPGA-based Softcore Processor. [Citation Graph (, )][DBLP]


  184. Coarse-grained reconfiguration. [Citation Graph (, )][DBLP]


  185. A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor. [Citation Graph (, )][DBLP]


  186. Application-specific reconfigurable processors. [Citation Graph (, )][DBLP]


  187. High-performance fpga-based floating-point adder with three inputs. [Citation Graph (, )][DBLP]


  188. An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. [Citation Graph (, )][DBLP]


  189. Towards a unique FPGA-based identification circuit using process variations. [Citation Graph (, )][DBLP]


  190. Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes. [Citation Graph (, )][DBLP]


  191. Reduction of Crosstalk Pessimism using Tendency Graph Approach. [Citation Graph (, )][DBLP]


  192. An Actor-Oriented Group Mobility Model for Wireless Ad Hoc Sensor Networks. [Citation Graph (, )][DBLP]


  193. TinyOS Extensions for a Wireless Sensor Network Node Based on a Dynamically Reconfigurable Processor. [Citation Graph (, )][DBLP]


  194. Flexible parallel pipeline network-on-chip based on dynamic packet identity management. [Citation Graph (, )][DBLP]


  195. Generation of Synthetic Floating-Point benchmark circuits. [Citation Graph (, )][DBLP]


  196. Functional modeling techniques for a wireless LAN OFDM transceiver. [Citation Graph (, )][DBLP]


  197. Process variations aware robust on-chip bus architecture synthesis for MPSoCs. [Citation Graph (, )][DBLP]


  198. Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects. [Citation Graph (, )][DBLP]


  199. PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels. [Citation Graph (, )][DBLP]


  200. Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II. [Citation Graph (, )][DBLP]


  201. A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support. [Citation Graph (, )][DBLP]


  202. Specification of alternative execution semantics of UML sequence diagrams within actor-oriented models. [Citation Graph (, )][DBLP]


  203. A simplified executable model to evaluate latency and throughput of networks-on-chip. [Citation Graph (, )][DBLP]


  204. An Efficient Fractional-Rate Interpolation Architecture. [Citation Graph (, )][DBLP]


  205. A Scalable Resampling Architecture. [Citation Graph (, )][DBLP]


  206. Validation of executable application models mapped onto network-on-chip platforms. [Citation Graph (, )][DBLP]


  207. Enabling self-reconfiguration on a video processing platform. [Citation Graph (, )][DBLP]


  208. Applying Communication Patterns to Actor-Oriented Models. [Citation Graph (, )][DBLP]


  209. Supporting Consistency Control between Functional and Structural Views in Interface-based Design Models. [Citation Graph (, )][DBLP]


  210. Configurable VLSI Architecture of a General Purpose Lifting-based Wavelet Processor. [Citation Graph (, )][DBLP]


  211. An Open VHDL-AMS Simulation Framework. [Citation Graph (, )][DBLP]


  212. An Actor-Oriented Model-Based Design Flow for Systems-on-Chip. [Citation Graph (, )][DBLP]


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