Journals in DBLP

IEEE Trans. VLSI Syst.
2001, volume: 9, number: 4

1. Shih-Arn Hwang, Cheng-Wen Wu
   Unified VLSI systolic array design for LZ data compression. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:489-499 [Journal]
   
2. T. D. Givargis, Frank Vahid, Jörg Henkel
   Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:500-508 [Journal]
   
3. Huesung Kim, Arun K. Somani, Akhilesh Tyagi
   A reconfigurable multifunction computing cache architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:509-523 [Journal]
   
4. Karsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
   FunState-an internal design representation for codesign. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:524-544 [Journal]
   
5. Adam J. Elbirt, W. Yip, B. Chetwynd, Christof Paar
   An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:545-557 [Journal]
   
6. M. Olivieri
   Correction to "design of synchronous and asynchronous variable-latency pipelined multipliers". [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:558-559 [Journal]