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Title:
Author:
Akhilesh Tyagi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pramod Ramarao, Akhilesh Tyagi
    An Adiabatic Framework for a Low Energy µ-Architecture & Compiler. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2003, pp:65-74 [Conf]
  2. Pramod Ramarao, Akhilesh Tyagi
    An Integrated Partitioning and Scheduling Based Branch Decoupling. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:252-268 [Conf]
  3. Ka-Ming Keung, Akhilesh Tyagi
    State space reconfigurability: an implementation architecture for self modifying finite automata. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:83-92 [Conf]
  4. Jun Ge, Soma Chaudhuri, Akhilesh Tyagi
    Control flow based obfuscation. [Citation Graph (0, 0)][DBLP]
    Digital Rights Management Workshop, 2005, pp:83-92 [Conf]
  5. Brian Blietz, Akhilesh Tyagi
    Software Tamper Resistance Through Dynamic Program Monitoring. [Citation Graph (0, 0)][DBLP]
    DRMTICS, 2005, pp:146-163 [Conf]
  6. Mahadevan Gomathisankaran, Akhilesh Tyagi
    TIVA: Trusted Integrity Verification Architecture. [Citation Graph (0, 0)][DBLP]
    DRMTICS, 2005, pp:13-31 [Conf]
  7. Deepali Deshpande, Arun K. Somani, Akhilesh Tyagi
    Hybrid Data/Configuration Caching for Striped FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:294-295 [Conf]
  8. Hue-Sung Kim, Arun K. Somani, Akhilesh Tyagi
    On Reconfiguring Cache for Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:296-297 [Conf]
  9. Deepali Deshpande, Arun K. Somani, Akhilesh Tyagi
    Configuration Caching Vs Data Caching for Striped FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:206-214 [Conf]
  10. Hue-Sung Kim, Arun K. Somani, Akhilesh Tyagi
    A reconfigurable multi-function computing cache architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:85-94 [Conf]
  11. John H. Reif, Akhilesh Tyagi
    Efficient Parallel Algorithms for Optical Computing with the DFT Primitive. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1990, pp:149-160 [Conf]
  12. Akhilesh Tyagi
    Energy-Time Trade-offs in VLSI Computation. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1989, pp:301-311 [Conf]
  13. Mahadevan Gomathisankaran, Akhilesh Tyagi
    Arc3D: A 3D Obfuscation Architecture. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:184-199 [Conf]
  14. Gyungho Lee, Akhilesh Tyagi
    Encoded Program Counter: Self-Protection from Buffer Overflow Attacks. [Citation Graph (0, 0)][DBLP]
    International Conference on Internet Computing, 2000, pp:387-394 [Conf]
  15. Akhilesh Tyagi
    VLSI design parsing (preliminary version). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:30-34 [Conf]
  16. Glenn Holt, Akhilesh Tyagi
    EPNR: an energy-efficient automated layout synthesis package. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:224-229 [Conf]
  17. Huesung Kim, Arun K. Somani, Akhilesh Tyagi
    Adaptive Balanced Computing (ABC) Microprocessor Using Reconfigurable Functional Caches (RFCs). [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:138-144 [Conf]
  18. Sriram Nadathur, Akhilesh Tyagi
    A Dependence Driven Efficient Dispatch Scheme. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:299-306 [Conf]
  19. Sriram Nadathur, Akhilesh Tyagi
    IPC Driven Dynamic Associative Cache Architecture for Low Energy. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:472-479 [Conf]
  20. Anshuman S. Nadkarni, Akhilesh Tyagi
    A Trace Based Evaluation of Speculative Branch Decoupling. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:300-0 [Conf]
  21. Vadhiraj Sankaranarayanan, Akhilesh Tyagi
    A Hierarchical Dependence Check and Folded Rename Mapping Based Scalable Dispatch Stage. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:249-255 [Conf]
  22. Akhilesh Tyagi, Hon-Chi Ng, Prasant Mohapatra
    Dynamic Branch Decoupled Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:442-0 [Conf]
  23. Akhilesh Tyagi
    Energy-Privacy Trade-Offs in VLSI Computations. [Citation Graph (0, 0)][DBLP]
    INDOCRYPT, 2005, pp:361-374 [Conf]
  24. H. Kumar, Magdy A. Bayoumi, Akhilesh Tyagi, Nam Ling, R. Kalyan
    Parallel Implementation of a Cut and Paste Maze Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2035-2038 [Conf]
  25. Akhilesh Tyagi
    Entropic bounds on FSM switching. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:323-328 [Conf]
  26. Vamshi Veeramachaneni, Akhilesh Tyagi, Suresh Rajgopal
    Re-encoding for low power state assignment of FSMs. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:173-178 [Conf]
  27. Glenn Holt, Akhilesh Tyagi
    Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:48-53 [Conf]
  28. Mahadevan Gomathisankaran, Akhilesh Tyagi
    WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:105-114 [Conf]
  29. Pramod Ramarao, Akhilesh Tyagi, Gyungho Lee
    Run-Time Support for Detection of Memory Access Violations to Prevent Buffer Overflow Exploits. [Citation Graph (0, 0)][DBLP]
    ISC, 2003, pp:366-380 [Conf]
  30. Ge Zhu, Akhilesh Tyagi
    Protection against Indirect Overflow Attacks on Pointers. [Citation Graph (0, 0)][DBLP]
    IWIA, 2004, pp:97-106 [Conf]
  31. Ka-Ming Keung, Akhilesh Tyagi
    SRAM CP: A Charge Recycling Design Schema for SRAM. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:95-106 [Conf]
  32. Vineela Manne, Akhilesh Tyagi
    An Adiabatic Charge Pump Based Charge Recycling Design Style. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:299-308 [Conf]
  33. Gyungho Lee, Akhilesh Tyagi
    Instruction-level Distributed Microarchitecture Based on Data Decoupling. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  34. Akhilesh Tyagi, John H. Reif
    Energy complexity of optical computations. [Citation Graph (0, 0)][DBLP]
    SPDP, 1990, pp:14-21 [Conf]
  35. M. K. Kidambi, Akhilesh Tyagi, Mohammed R. Madani, Magdy A. Bayoumi
    Parameterized Modeling of Open-Circuit Critical Volume for Three-Dimensional Defects in VLSI Processing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:333-338 [Conf]
  36. Akhilesh Tyagi
    A Module Generator Development Environment: Area Estimation and Design-Space Exploration Encapsulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:214-217 [Conf]
  37. Mahadevan Gomathisankaran, Akhilesh Tyagi
    Architecture Support for 3D Obfuscation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:5, pp:497-507 [Journal]
  38. Akhilesh Tyagi
    A Reduced-Area Scheme for Carry-Select Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:10, pp:1163-1170 [Journal]
  39. M. K. Kidambi, Akhilesh Tyagi, Mohammed R. Madani, Magdy A. Bayoumi
    Three-dimensional defect sensitivity modeling for open circuits in ULSI structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:366-371 [Journal]
  40. Sonal Pandey, Arun K. Somani, Akhilesh Tyagi
    Intermediate processing protocol for processing within IP-routed networks. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2003, v:27, n:5-6, pp:285-295 [Journal]
  41. Ka-Ming Keung, Vineela Manne, Akhilesh Tyagi
    A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:733-745 [Journal]
  42. Huesung Kim, Arun K. Somani, Akhilesh Tyagi
    A reconfigurable multifunction computing cache architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:509-523 [Journal]
  43. Mahadevan Gomathisankaran, Akhilesh Tyagi
    WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:388-400 [Journal]

  44. Low power FSM design using Huffman-style encoding. [Citation Graph (, )][DBLP]


  45. An algebraic model for design space with applications to function module generation. [Citation Graph (, )][DBLP]


  46. REBEL - Reconfigurable Block Encryption Logic. [Citation Graph (, )][DBLP]


  47. Relating Boolean gate truth tables to one-way functions. [Citation Graph (, )][DBLP]


  48. Preventing IC Piracy Using Reconfigurable Logic Barriers. [Citation Graph (, )][DBLP]


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