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Matthias Gries: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sören Sonntag, Matthias Gries, Christian Sauer
    Performance Evaluation of Packet Processing Architectures Using Multiclass Queuing Networks. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 2006, pp:80-89 [Conf]
  2. Chidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer
    Programming challenges in network processor deployment. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:178-187 [Conf]
  3. Scott J. Weber, Matthew W. Moskewicz, Matthias Gries, Christian Sauer, Kurt Keutzer
    Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:18-23 [Conf]
  4. Christian Sauer, Matthias Gries, Sören Sonntag
    Modular domain-specific implementation and exploration framework for embedded software platforms. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:254-259 [Conf]
  5. Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Künzli
    A framework for evaluating design tradeoffs in packet processing architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:880-885 [Conf]
  6. Matthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer
    Comparing Analytical Modeling with Simulation for Network Processors: A Case Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20256-20261 [Conf]
  7. Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Alexander Maxiaguine, Jonas Greutert
    Embedded Software in Network Processors - Models and Algorithms. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2001, pp:416-434 [Conf]
  8. Matthias Gries
    The Impact of Recent DRAM Architectures on Embedded Systems Performance. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1282-0 [Conf]
  9. Hans-Martin Blüthgen, Christian Sauer, Dominik Langen, Matthias Gries, Wolfgang Raab
    Application-Driven Design of Cost-Efficient Communications Platforms. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:314-318 [Conf]
  10. Sören Sonntag, Matthias Gries, Christian Sauer
    Performance Evaluation of VLSI platforms using SystemQ. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (1), 2005, pp:319-323 [Conf]
  11. Christian Sauer, Matthias Gries, Sören Sonntag
    Modular Reference Implementation of an IP-DSLAM. [Citation Graph (0, 0)][DBLP]
    ISCC, 2005, pp:191-198 [Conf]
  12. Christian Sauer, Matthias Gries, Sören Sonntag, Dietmar Tolle, Bo Wu, Rudi Knorr
    Trends in Access Networks and their Implementation in DSLAMs. [Citation Graph (0, 0)][DBLP]
    LCN, 2005, pp:493-494 [Conf]
  13. Christian Sauer, Matthias Gries, J.-C. Niemann, M. Porrmann, M. Thies
    Application-Driven Development of Concurrent Packet Processing Platforms. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2006, pp:55-61 [Conf]
  14. Christian Sauer, Matthias Gries, José Ignacio Gómez, Scott J. Weber, Kurt Keutzer
    Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:129-134 [Conf]
  15. Samarjit Chakraborty, Matthias Gries, Lothar Thiele
    Supporting a Low Delay Best-Effort Class in the Presence of Real-Time Traffic. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2002, pp:45-54 [Conf]
  16. Sören Sonntag, Matthias Gries, Christian Sauer
    SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:434-444 [Conf]
  17. Matthias Gries
    Methods for evaluating and covering the design space during early design development. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:2, pp:131-183 [Journal]
  18. Christian Sauer, Matthias Gries, Sebastian Dirk
    Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1102-1107 [Conf]
  19. Karsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
    FunState-an internal design representation for codesign. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:524-544 [Journal]

  20. SystemClick: a domain-specific framework for early exploration using functional performance models. [Citation Graph (, )][DBLP]

  21. A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores. [Citation Graph (, )][DBLP]

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