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Jörg Henkel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jürgen Becker, Kurt Brändle, Uwe Brinkschulte, Jörg Henkel, Wolfgang Karl, Thorsten Köster, Michael Wenz, Heinz Wörn
    Digital On-Demand Computing Organism for Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:230-245 [Conf]
  2. Newton Cheung, Sri Parameswaran, Jörg Henkel
    Battery-aware instruction generation for embedded processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:553-556 [Conf]
  3. Tony Givargis, Frank Vahid, Jörg Henkel
    A hybrid approach for core-based system-level power modeling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:141-146 [Conf]
  4. Tony Givargis, Frank Vahid, Jörg Henkel
    Trace-driven system-level power evaluation of system-on-a-chip peripheral cores. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:306-312 [Conf]
  5. Jörg Henkel, Rolf Ernst
    High-Level Estimation Techniques for Usage in Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:353-360 [Conf]
  6. Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel
    A flexible framework for communication evaluation in SoC design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:956-959 [Conf]
  7. Haris Lekatsas, Jörg Henkel
    ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:113-120 [Conf]
  8. Jörg Henkel, Rolf Ernst
    The Interplay of Run-Time Estimation and Granularity in HW/SW Partitioning. [Citation Graph (0, 0)][DBLP]
    CODES, 1996, pp:52-61 [Conf]
  9. Jörg Henkel, Yanbing Li
    Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:23-27 [Conf]
  10. Dirk Herrmann, Jörg Henkel, Rolf Ernst
    An approach to the adaptation of estimated cost parameters in the COSYMA system. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:100-107 [Conf]
  11. Haris Lekatsas, Jörg Henkel, Wayne Wolf
    Code compression as a variable in hardware/software co-design. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:120-124 [Conf]
  12. Mohammad Abdullah Al Faruque, Gereon Weiss, Jörg Henkel
    Bounded arbitration algorithm for QoS-supported on-chip communication. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:76-81 [Conf]
  13. Yanbing Li, Jörg Henkel
    A Framework for Estimation and Minimizing Energy Dissipation of Embedded HW/SW Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:188-193 [Conf]
  14. Jörg Henkel
    A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:122-127 [Conf]
  15. Jörg Henkel, Rolf Ernst
    A Hardware/Software Partitioner Using a Dynamically Determined Granularity. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:691-696 [Conf]
  16. Jörg Henkel, Haris Lekatsas
    A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:744-749 [Conf]
  17. Haris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula, Murugan Sankaradass
    CoCo: a hardware/software platform for rapid prototyping of code compression technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:306-311 [Conf]
  18. Haris Lekatsas, Jörg Henkel, Venkata Jakkula
    Design of an one-cycle decompression hardware for performance increase in embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:34-39 [Conf]
  19. Haris Lekatsas, Jörg Henkel, Wayne Wolf
    Code compression for low power embedded system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:294-299 [Conf]
  20. Newton Cheung, Jörg Henkel, Sri Parameswaran
    Rapid Configuration and Instruction Selection for an ASIP: A Case Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10802-10809 [Conf]
  21. Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan
    MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1020-1027 [Conf]
  22. Jörg Henkel, Tony Givargis, Frank Vahid
    Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:333-0 [Conf]
  23. Tin-Man Lee, Wayne Wolf, Jörg Henkel
    Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:296-301 [Conf]
  24. Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf
    Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10542-10549 [Conf]
  25. Tiehan Lv, Wayne Wolf, Jörg Henkel, Haris Lekatsas
    An Adaptive Dictionary Encoding Scheme for SOC Data Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1059- [Conf]
  26. Radu Marculescu, Massoud Pedram, Jörg Henkel
    Distributed Multimedia System Design: A Holistic Perspective. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1342-1349 [Conf]
  27. Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv
    A Case Study in Networks-on-Chip Design for Embedded Video. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:770-777 [Conf]
  28. Haris Lekatsas, Wayne Wolf, Jörg Henkel
    Arithmetic Coding for Low Power Embedded System Design. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 2000, pp:430-439 [Conf]
  29. Talal Bonny, Jörg Henkel
    Using Lin-Kernighan algorithm for look-up table compression to improve code density. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:259-265 [Conf]
  30. Jörg Henkel
    A Methodology for Minimizing Power Dissipation of Embedded Systems through Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:86-0 [Conf]
  31. Newton Cheung, Sri Parameswaran, Jörg Henkel
    INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:291-298 [Conf]
  32. Newton Cheung, Sri Parameswaran, Jörg Henkel
    A quantitative study and estimation models for extensible instructions in embedded processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:183-189 [Conf]
  33. Tony Givargis, Jörg Henkel, Frank Vahid
    Interface and cache power exploration for core-based embedded system design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:270-273 [Conf]
  34. Tony Givargis, Frank Vahid, Jörg Henkel
    System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:25-30 [Conf]
  35. Jörg Henkel, Rolf Ernst, Ulrich Holtmann, Thomas Benner
    Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:96-100 [Conf]
  36. Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel
    LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:518-522 [Conf]
  37. Sri Parameswaran, Jörg Henkel
    I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:635-0 [Conf]
  38. Haris Lekatsas, Jörg Henkel, Wayne Wolf
    A Decompression Architecture for Low Power Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:571-574 [Conf]
  39. W. Ye, Rolf Ernst, Thomas Benner, Jörg Henkel
    Fast Timing Analysis for Hardware-Software Co-Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:452-457 [Conf]
  40. Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar
    A methodology for design, modeling, and analysis of networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1778-1781 [Conf]
  41. Haris Lekatsas, Jörg Henkel, Wayne Wolf
    Design and simulation of a pipelined decompression architecture for embedded systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:63-68 [Conf]
  42. Tony Givargis, Frank Vahid, Jörg Henkel
    Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:163-171 [Conf]
  43. Jörg Henkel, Rolf Ernst
    A path-based technique for estimating hardware runtime in HW/SW-cosynthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:116-121 [Conf]
  44. Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran
    Specification and Design of Multi-Million Gate SOCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:18-19 [Conf]
  45. Jörg Henkel, Wayne Wolf, Srimat T. Chakradhar
    On-chip networks: A scalable, communication-centric embedded system design paradigm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:845-0 [Conf]
  46. Haris Lekatsas, Jörg Henkel
    ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:113-120 [Conf]
  47. Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar
    A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:117-123 [Conf]
  48. Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar
    Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:639-644 [Conf]
  49. Jörg Henkel
    Closing the SoC Design Gap. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:9, pp:119-121 [Journal]
  50. Jörg Henkel, Xiaobo Hu, Shuvra S. Bhattacharyya
    Guest Editors' Introduction: Taking on the Embedded System Design Challenge. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:4, pp:35-37 [Journal]
  51. Rolf Ernst, Jörg Henkel, Thomas Benner
    Hardware-Software Cosynthesis for Microcontrollers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:4, pp:64-75 [Journal]
  52. Haris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula
    Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:5, pp:406-415 [Journal]
  53. Tiehan Lv, Jiang Xu, Wayne Wolf, Burak Ozer, Jörg Henkel, Srimat T. Chakradhar
    A Methodology for Architectural Design of Multimedia Multiprocessor SoCs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:1, pp:18-26 [Journal]
  54. Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar
    A design methodology for application-specific networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:263-280 [Journal]
  55. Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel
    Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:69-80 [Journal]
  56. Haris Lekatsas, Jörg Henkel, Wayne Wolf
    Approximate arithmetic coding for bus transition reduction in low power designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:696-707 [Journal]
  57. Talal Bonny, Jörg Henkel
    Instruction Splitting for Efficient Code Compression. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:646-651 [Conf]
  58. Lars Bauer, Muhammad Shafique, Simon Kramer 0002, Jörg Henkel
    RISPP: Rotating Instruction Set Processing Platform. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:791-796 [Conf]
  59. Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel
    Instruction trace compression for rapid instruction cache simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:803-808 [Conf]
  60. Talal Bonny, Jörg Henkel
    Efficient code density through look-up table compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:809-814 [Conf]
  61. Lars Bauer, Muhammad Shafique, Dirk Teufel, Jörg Henkel
    A Self-Adaptive Extensible Embedded Processor. [Citation Graph (0, 0)][DBLP]
    SASO, 2007, pp:344-350 [Conf]
  62. T. D. Givargis, Frank Vahid, Jörg Henkel
    Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:4, pp:500-508 [Journal]
  63. Tony Givargis, Frank Vahid, Jörg Henkel
    Instruction-based system-level power evaluation of system-on-a-chip peripheral cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:856-863 [Journal]
  64. Jörg Henkel, Yanbing Li
    Avalanche: an environment for design space exploration and optimization of low-power embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:454-468 [Journal]
  65. Tony Givargis, Frank Vahid, Jörg Henkel
    System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:416-422 [Journal]
  66. Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf
    A dictionary-based en/decoding scheme for low-power data buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:943-951 [Journal]

  67. Transaction Specific Virtual Channel Allocation in QoS Supported On-chip Communication. [Citation Graph (, )][DBLP]


  68. Block cache for embedded systems. [Citation Graph (, )][DBLP]


  69. MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. [Citation Graph (, )][DBLP]


  70. Run-time instruction set selection in a transmutable embedded processor. [Citation Graph (, )][DBLP]


  71. ADAM: run-time agent-based distributed application mapping for on-chip communication. [Citation Graph (, )][DBLP]


  72. LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors. [Citation Graph (, )][DBLP]


  73. Instruction Re-encoding Facilitating Dense Embedded Code. [Citation Graph (, )][DBLP]


  74. Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures. [Citation Graph (, )][DBLP]


  75. Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set. [Citation Graph (, )][DBLP]


  76. Cross-architectural design space exploration tool for reconfigurable processors. [Citation Graph (, )][DBLP]


  77. A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec. [Citation Graph (, )][DBLP]


  78. Efficient constant-time entropy decoding for H.264. [Citation Graph (, )][DBLP]


  79. Configurable links for runtime adaptive on-chip communication. [Citation Graph (, )][DBLP]


  80. RMOT: Recursion in model order for task execution time estimation in a software pipeline. [Citation Graph (, )][DBLP]


  81. KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture. [Citation Graph (, )][DBLP]


  82. enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder. [Citation Graph (, )][DBLP]


  83. An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode Exclusion. [Citation Graph (, )][DBLP]


  84. DAGS: Distribution agnostic sequential Monte Carlo scheme for task execution time estimation. [Citation Graph (, )][DBLP]


  85. An Optimized Application Architecture of the H.264 Video Encoder for Application Specific Platforms. [Citation Graph (, )][DBLP]


  86. A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor. [Citation Graph (, )][DBLP]


  87. RISPP: A run-time adaptive reconfigurable embedded processor. [Citation Graph (, )][DBLP]


  88. Run-time adaptive on-chip communication scheme. [Citation Graph (, )][DBLP]


  89. ROAdNoC: runtime observability for an adaptive network on chip architecture. [Citation Graph (, )][DBLP]


  90. FBT: filled buffer technique to reduce code size for VLIW processors. [Citation Graph (, )][DBLP]


  91. TAPE: Thermal-aware agent-based power econom multi/many-core architectures. [Citation Graph (, )][DBLP]


  92. REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set. [Citation Graph (, )][DBLP]


  93. Non-linear rate control for H.264/AVC video encoder with multiple picture types using image-statistics and motion-based Macroblock Prioritization. [Citation Graph (, )][DBLP]


  94. H.264 HDTV Decoder Using Application-Specific Networks-On-Chip. [Citation Graph (, )][DBLP]


  95. 3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding. [Citation Graph (, )][DBLP]


  96. Security and Dependability of Embedded Systems: A Computer Architects' Perspective. [Citation Graph (, )][DBLP]


  97. Dependability and Security Will Change Embedded Computing. [Citation Graph (, )][DBLP]


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