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Publications of Author

1. Jörg Henkel, Yanbing Li
   Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder. [Citation Graph (0, 0)][DBLP]
   CODES, 1998, pp:23-27 [Conf]
   
2. Yanbing Li, Jörg Henkel
   A Framework for Estimation and Minimizing Energy Dissipation of Embedded HW/SW Systems. [Citation Graph (0, 0)][DBLP]
   DAC, 1998, pp:188-193 [Conf]
   
3. Yanbing Li, Tim Callahan, Ervan Darnell, Randolph E. Harr, Uday Kurkure, Jon Stockwood
   Hardware-software co-design of embedded reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:507-512 [Conf]
   
4. Yanbing Li, Wayne Wolf
   A Task-Level Hierarchical Memory Model for System Synthesis of Multiprocessors. [Citation Graph (0, 0)][DBLP]
   DAC, 1997, pp:153-156 [Conf]
   
5. Yanbing Li, Wayne Wolf
   Hardware/software co-synthesis with memory hierarchies. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1998, pp:430-436 [Conf]
   
6. Yanbing Li, Miodrag Potkonjak, Wayne Wolf
   Real-Time Operating Systems for Embedded Computing. [Citation Graph (0, 0)][DBLP]
   ICCD, 1997, pp:388-392 [Conf]
   
7. Yanbing Li, Bo Tao, Shun Kei, Wayne Wolf
   Semantic Image Retrieval Through Human Subject Segmentation and Characterization. [Citation Graph (0, 0)][DBLP]
   Storage and Retrieval for Image and Video Databases (SPIE), 1997, pp:340-351 [Conf]
   
8. Yanbing Li, Wayne Wolf
   Hardware/software co-synthesis with memory hierarchies. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1405-1417 [Journal]
   
9. Yanbing Li, Miriam Leeser
   HML, a novel hardware description language and its translation to VHDL. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:1-8 [Journal]
   
10. Jörg Henkel, Yanbing Li
    Avalanche: an environment for design space exploration and optimization of low-power embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:454-468 [Journal]
    
11. 
    Hierarchical scheduling and allocation of multirate systems on heterogeneous multiprocessors. [Citation Graph (, )][DBLP]