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Miodrag Potkonjak :
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Nathan Shnidman , William H. Mangione-Smith , Miodrag Potkonjak Fault Scanner for Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] ARVLSI, 1997, pp:238-255 [Conf ] Inki Hong , Darko Kirovski , Miodrag Potkonjak , Marios C. Papaefthymiou Symbolic debugging of globally optimized behavioral specifications. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2000, pp:397-400 [Conf ] Inki Hong , Miodrag Potkonjak Techniques for Functional Test Pattern Execution. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 1998, pp:283-288 [Conf ] Inki Hong , Miodrag Potkonjak , Ramesh Karri Heterogeneous BISR-approach using System Level Synthesis Flexibility. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 1998, pp:289-294 [Conf ] Johnson S. Kin , Chunho Lee , William H. Mangione-Smith , Miodrag Potkonjak A technique for QoS-based system partitioning. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2000, pp:241-246 [Conf ] Darko Kirovski , Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith Synthesis of Power Efficient Systems-on-Silicon. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 1998, pp:557-562 [Conf ] Chunho Lee , Miodrag Potkonjak Quantitative Selection of Media Benchmarks. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 1998, pp:105-110 [Conf ] Miodrag Potkonjak , Sujit Dey , Rabindra K. Roy Synthesis-for-testability using transformations. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 1995, pp:- [Conf ] Gang Qu , Jennifer L. Wong , Miodrag Potkonjak Fair watermarking techniques. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2000, pp:55-60 [Conf ] Darko Kirovski , Milenko Drinic , Miodrag Potkonjak Enabling trusted software integrity. [Citation Graph (0, 0)][DBLP ] ASPLOS, 2002, pp:108-120 [Conf ] Andrew E. Caldwell , Hyun-Jin Choi , Andrew B. Kahng , Stefanus Mantik , Miodrag Potkonjak , Gang Qu , Jennifer L. Wong Effective Iterative Techniques for Fingerprinting Design IP. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:843-848 [Conf ] Srimat T. Chakradhar , Sujit Dey , Miodrag Potkonjak , Steven G. Rothweiler Sequential Circuit Delay optimization Using Global Path Delays. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:483-489 [Conf ] Y. G. DeCastelo-Vide-e-Souza , Miodrag Potkonjak , Alice C. Parker Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming. [Citation Graph (0, 0)][DBLP ] DAC, 1995, pp:113-118 [Conf ] Milos D. Ercegovac , Darko Kirovski , Miodrag Potkonjak Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:568-573 [Conf ] Lisa Guerra , Miodrag Potkonjak , Jan M. Rabaey A Methodology for Guided Behavioral-Level Optimization. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:309-314 [Conf ] Inki Hong , Darko Kirovski , Miodrag Potkonjak Potential-Driven Statistical Ordering of Transformations. [Citation Graph (0, 0)][DBLP ] DAC, 1997, pp:347-352 [Conf ] Inki Hong , Darko Kirovski , Gang Qu , Miodrag Potkonjak , Mani B. Srivastava Power Optimization of Variable Voltage Core-Based Systems. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:176-181 [Conf ] Inki Hong , Miodrag Potkonjak Behavioral Synthesis Techniques for Intellectual Property Protection. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:849-854 [Conf ] Zia Iqbal , Miodrag Potkonjak , Sujit Dey , Alice C. Parker Critical Path Minimization Using Retiming and Algebraic Speed-Up. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:573-577 [Conf ] Andrew B. Kahng , John Lach , William H. Mangione-Smith , Stefanus Mantik , Igor L. Markov , Miodrag Potkonjak , Paul Tucker , Huijuan Wang , Gregory Wolfe Watermarking Techniques for Intellectual Property Protection. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:776-781 [Conf ] Andrew B. Kahng , Stefanus Mantik , Igor L. Markov , Miodrag Potkonjak , Paul Tucker , Huijuan Wang , Gregory Wolfe Robust IP Watermarking Methodologies for Physical Design. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:782-787 [Conf ] Kyosun Kim , Ramesh Karri , Miodrag Potkonjak Synthesis of Application Specific Programmable Processors. [Citation Graph (0, 0)][DBLP ] DAC, 1997, pp:353-358 [Conf ] Johnson Kin , Chunho Lee , William H. Mangione-Smith , Miodrag Potkonjak Power Efficient Mediaprocessors: Design Space Exploration. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:321-326 [Conf ] Darko Kirovski , Milenko Drinic , Miodrag Potkonjak Hypermedia-Aided Design. [Citation Graph (0, 0)][DBLP ] DAC, 2001, pp:407-412 [Conf ] Darko Kirovski , David T. Liu , Jennifer L. Wong , Miodrag Potkonjak Forensic engineering techniques for VLSI CAD tools. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:581-586 [Conf ] Darko Kirovski , Miodrag Potkonjak System-Level Synthesis of Low-Power Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP ] DAC, 1997, pp:697-702 [Conf ] Darko Kirovski , Miodrag Potkonjak Efficient Coloring of a Large Spectrum of Graphs. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:427-432 [Conf ] Darko Kirovski , Miodrag Potkonjak Engineering Change: Methodology and Applications to Behavioral and System Synthesis. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:604-609 [Conf ] Farinaz Koushanfar , Jennifer L. Wong , Jessica Feng , Miodrag Potkonjak ILP-based engineering change. [Citation Graph (0, 0)][DBLP ] DAC, 2002, pp:910-915 [Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Efficient error detection, localization, and correction for FPGA-based debugging. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:207-212 [Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Robust FPGA Intellectual Property Protection Through Multiple Small Watermarks. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:831-836 [Conf ] Kumar N. Lalgudi , Marios C. Papaefthymiou , Miodrag Potkonjak Optimizing Systems for Effective Block-Processing: The k -Delay Problem. [Citation Graph (0, 0)][DBLP ] DAC, 1996, pp:714-719 [Conf ] Chunho Lee , Johnson Kin , Miodrag Potkonjak , William H. Mangione-Smith Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:321-326 [Conf ] Seapahn Megerian , Milenko Drinic , Miodrag Potkonjak Watermarking integer linear programming solutions. [Citation Graph (0, 0)][DBLP ] DAC, 2002, pp:8-13 [Conf ] Seapahn Meguerdichian , Farinaz Koushanfar , Advait Mogre , Dusan Petranovic , Miodrag Potkonjak MetaCores: Design and Optimization Techniques. [Citation Graph (0, 0)][DBLP ] DAC, 2001, pp:585-590 [Conf ] Seapahn Meguerdichian , Miodrag Potkonjak Watermarking while preserving the critical path. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:108-111 [Conf ] Gang Qu , Miodrag Potkonjak Fingerprinting intellectual property using constraint-addition. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:587-592 [Conf ] Miodrag Potkonjak , Sujit Dey Optimizing Resource Utilization and Testability Using Hot Potato Techniques. [Citation Graph (0, 0)][DBLP ] DAC, 1994, pp:201-205 [Conf ] Miodrag Potkonjak , Kyosun Kim , Ramesh Karri Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study. [Citation Graph (0, 0)][DBLP ] DAC, 1997, pp:252-257 [Conf ] Miodrag Potkonjak , Mani B. Srivastava Rephasing: A Transformation Technique for the Manipulation of Timing Constraints. [Citation Graph (0, 0)][DBLP ] DAC, 1995, pp:107-112 [Conf ] Miodrag Potkonjak , Mani B. Srivastava , Anantha Chandrakasan Efficient Substitution of Multiple Constant Multiplications by Shifts and Additions Using Iterative Pairwise Matching. [Citation Graph (0, 0)][DBLP ] DAC, 1994, pp:189-194 [Conf ] Gang Qu , Naoyuki Kawabe , Kimiyoshi Usami , Miodrag Potkonjak Function-level power estimation methodology for microprocessors. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:810-813 [Conf ] Gang Qu , Jennifer L. Wong , Miodrag Potkonjak Optimization-Intensive Watermarking Techniques for Decision Problems. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:33-36 [Conf ] Mani B. Srivastava , Miodrag Potkonjak Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based Approach. [Citation Graph (0, 0)][DBLP ] DAC, 1996, pp:343-348 [Conf ] Gregory Wolfe , Jennifer L. Wong , Miodrag Potkonjak Watermarking Graph Partitioning Solutions. [Citation Graph (0, 0)][DBLP ] DAC, 2001, pp:486-489 [Conf ] Jennifer L. Wong , Farinaz Koushanfar , Miodrag Potkonjak Flexible ASIC: shared masking for multiple media processors. [Citation Graph (0, 0)][DBLP ] DAC, 2005, pp:909-914 [Conf ] Jennifer L. Wong , Seapahn Megerian , Miodrag Potkonjak Forward-looking objective functions: concept & applications in high level synthesis. [Citation Graph (0, 0)][DBLP ] DAC, 2002, pp:904-909 [Conf ] Jennifer L. Wong , Seapahn Megerian , Miodrag Potkonjak Design techniques for sensor appliances: foundations and light compass case study. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:66-71 [Conf ] Jennifer L. Wong , Weiping Liao , Fei Li , Lei He , Miodrag Potkonjak Scheduling of Soft Real-Time Systems for Context-Aware Applications. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:318-323 [Conf ] Milenko Drinic , Darko Kirovski , Miodrag Potkonjak PPM Model Cleaning. [Citation Graph (0, 0)][DBLP ] DCC, 2003, pp:163-172 [Conf ] Jessica Feng , Lewis Girod , Miodrag Potkonjak Consistency-Based On-line Localization in Sensor Networks. [Citation Graph (0, 0)][DBLP ] DCOSS, 2006, pp:529-545 [Conf ] Lisa Guerra , Miodrag Potkonjak , Jan M. Rabaey High Level Synthesis Techniques for Efficient Built-In-Self Repair. [Citation Graph (0, 0)][DBLP ] DFT, 1993, pp:41-48 [Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures. [Citation Graph (0, 0)][DBLP ] DFT, 1999, pp:386-394 [Conf ] Mani B. Srivastava , Miodrag Potkonjak Transforming Linear Systems for Joint Latency and Throughout Optimization. [Citation Graph (0, 0)][DBLP ] EDAC-ETC-EUROASIC, 1994, pp:267-271 [Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Efficiently Supporting Fault-Tolerance in FPGAs. [Citation Graph (0, 0)][DBLP ] FPGA, 1998, pp:105-115 [Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Efficient Support of Hardware Debugging Through FPGA Physical Design Partitioning. [Citation Graph (0, 0)][DBLP ] FPGA, 1999, pp:247- [Conf ] Anantha Chandrakasan , Miodrag Potkonjak , Jan M. Rabaey , Robert W. Brodersen HYPER-LP: a system for power minimization using architectural transformations. [Citation Graph (0, 0)][DBLP ] ICCAD, 1992, pp:300-303 [Conf ] Miguel R. Corazao , Marwan A. Khalaf , Lisa M. Guerra , Miodrag Potkonjak , Jan M. Rabaey Instruction set mapping for performance optimization. [Citation Graph (0, 0)][DBLP ] ICCAD, 1993, pp:518-521 [Conf ] Sujit Dey , Vijay Gangaram , Miodrag Potkonjak A controller-based design-for-testability technique for controller-data path circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1995, pp:534-540 [Conf ] Sujit Dey , Miodrag Potkonjak Non-scan design-for-testability of RT-level data paths. [Citation Graph (0, 0)][DBLP ] ICCAD, 1994, pp:640-645 [Conf ] Sujit Dey , Miodrag Potkonjak , Steven G. Rothweiler Performance optimization of sequential circuits by eliminating retiming bottlenecks. [Citation Graph (0, 0)][DBLP ] ICCAD, 1992, pp:504-509 [Conf ] Sujit Dey , Miodrag Potkonjak , Rabindra K. Roy Exploiting hardware sharing in high-level synthesis for partial scan optimization. [Citation Graph (0, 0)][DBLP ] ICCAD, 1993, pp:20-25 [Conf ] Milenko Drinic , Darko Kirovski , Seapahn Meguerdichian , Miodrag Potkonjak Latency-Guided On-Chip Bus Network Design. [Citation Graph (0, 0)][DBLP ] ICCAD, 2000, pp:420-423 [Conf ] Lisa Guerra , Miodrag Potkonjak , Jan M. Rabaey High level synthesis for reconfigurable datapath structures. [Citation Graph (0, 0)][DBLP ] ICCAD, 1993, pp:26-29 [Conf ] Inki Hong , Miodrag Potkonjak Power optimization in disk-based real-time application specific systems. [Citation Graph (0, 0)][DBLP ] ICCAD, 1996, pp:634-637 [Conf ] Inki Hong , Miodrag Potkonjak , Lisa Guerra Throughput optimization of general non-linear computations. [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:406-409 [Conf ] Inki Hong , Miodrag Potkonjak , Ramesh Karri Power optimization using divide-and-conquer techniques for minimization of the number of operations. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:108-111 [Conf ] Inki Hong , Miodrag Potkonjak , Mani B. Srivastava On-line scheduling of hard real-time tasks on variable voltage processor. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:653-656 [Conf ] Serge Hustin , Miodrag Potkonjak , Eric Verhulst , Wayne Wolf Real-time operating systems for embedded computing. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:2- [Conf ] Andrew B. Kahng , Darko Kirovski , Stefanus Mantik , Miodrag Potkonjak , Jennifer L. Wong Copy detection for intellectual property protection of VLSI designs. [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:600-605 [Conf ] Farinaz Koushanfar , Darko Kirovski , Miodrag Potkonjak Symbolic Debugging Scheme for Optimized Hardware and Software. [Citation Graph (0, 0)][DBLP ] ICCAD, 2000, pp:40-43 [Conf ] Kyosun Kim , Ramesh Karri , Miodrag Potkonjak Heterogeneous built-in resiliency of application specific programmable processors. [Citation Graph (0, 0)][DBLP ] ICCAD, 1996, pp:406-411 [Conf ] Kyosun Kim , Ramesh Karri , Miodrag Potkonjak Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:33-38 [Conf ] Darko Kirovski , Yean-Yow Hwang , Miodrag Potkonjak , Jason Cong Intellectual property protection by watermarking combinational logic synthesis solutions. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:194-198 [Conf ] Darko Kirovski , Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith Application-driven synthesis of core-based systems. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:104-107 [Conf ] Darko Kirovski , Miodrag Potkonjak A quantitative approach to functional debugging. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:170-173 [Conf ] Darko Kirovski , Miodrag Potkonjak Localized watermarking: methodology and application to operation scheduling. [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:596-599 [Conf ] Darko Kirovski , Miodrag Potkonjak , Lisa Guerra Functional debugging of systems-on-chip. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:525-528 [Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Signature hiding techniques for FPGA intellectual property protection. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:186-189 [Conf ] Chunho Lee , Miodrag Potkonjak A quantitative approach to development and validation of synthetic benchmarks for behavioral synthesis. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:347-351 [Conf ] Gang Qu , Miodrag Potkonjak Analysis of watermarking techniques for graph coloring problem. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:190-193 [Conf ] Gang Qu , Miodrag Potkonjak Power minimization using system-level partitioning of applications with quality of service requirements. [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:343-346 [Conf ] Miodrag Potkonjak , Sujit Dey , Kazutoshi Wakabayashi Design-for-debugging of application specific designs. [Citation Graph (0, 0)][DBLP ] ICCAD, 1995, pp:295-301 [Conf ] Miodrag Potkonjak , Jan M. Rabaey Optimizing Resource Utilization Using Transformations. [Citation Graph (0, 0)][DBLP ] ICCAD, 1991, pp:88-91 [Conf ] Miodrag Potkonjak , Jan M. Rabaey Maximally fast and arbitrarily fast implementation of linear computations. [Citation Graph (0, 0)][DBLP ] ICCAD, 1992, pp:304-308 [Conf ] Miodrag Potkonjak , Jan M. Rabaey Algorithm selection: a quantitative computation-intensive optimization approach. [Citation Graph (0, 0)][DBLP ] ICCAD, 1994, pp:90-95 [Conf ] Miodrag Potkonjak , Wayne Wolf Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques. [Citation Graph (0, 0)][DBLP ] ICCAD, 1995, pp:446-451 [Conf ] Gang Qu , Miodrag Potkonjak Techniques for energy minimization of communication pipelines. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:597-600 [Conf ] Jan M. Rabaey , Miodrag Potkonjak , Farinaz Koushanfar , Suet-Fei Li , Tim Tuan Challenges and Opportunities in Broadband and Wireless Communication Designs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2000, pp:76-82 [Conf ] Jennifer L. Wong , Azadeh Davoodi , Vishal Khandelwal , Ankur Srivastava , Miodrag Potkonjak Wire-length prediction using statistical techniques. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:702-705 [Conf ] Jennifer L. Wong , Farinaz Koushanfar , Seapahn Meguerdichian , Miodrag Potkonjak A Probabilistic Constructive Approach to Optimization Problems. [Citation Graph (0, 0)][DBLP ] ICCAD, 2001, pp:453-0 [Conf ] Zhiru Zhang , Yiping Fan , Miodrag Potkonjak , Jason Cong Gradual Relaxation Techniques with Applications to Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] ICCAD, 2003, pp:529-535 [Conf ] Jessica Feng , Farinaz Koushanfar , Miodrag Potkonjak System-Architectures for Sensor Networks Issues, Alternatives, and Directions. [Citation Graph (0, 0)][DBLP ] ICCD, 2002, pp:226-0 [Conf ] Farinaz Koushanfar , Miodrag Potkonjak , Vandana Prabhu , Jan M. Rabaey Processors for Mobile Applications. [Citation Graph (0, 0)][DBLP ] ICCD, 2000, pp:603-608 [Conf ] Yanbing Li , Miodrag Potkonjak , Wayne Wolf Real-Time Operating Systems for Embedded Computing. [Citation Graph (0, 0)][DBLP ] ICCD, 1997, pp:388-392 [Conf ] Miodrag Potkonjak , Sujit Dey , Zia Iqbal , Alice C. Parker High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques. [Citation Graph (0, 0)][DBLP ] ICCD, 1993, pp:498-504 [Conf ] Miodrag Potkonjak Discrete-relaxation-based heuristic techniques for video algorithm/architecture matching and system level transformations. [Citation Graph (0, 0)][DBLP ] ICIP, 1995, pp:77-80 [Conf ] Miodrag Potkonjak , Anantha Chandrakasan Synthesis and selection of DCT algorithms using behavioral synthesis-based algorithm space exploration. [Citation Graph (0, 0)][DBLP ] ICIP, 1995, pp:65-68 [Conf ] Gang Qu , Miodrag Potkonjak Hiding Signatures in Graph Coloring Solutions. [Citation Graph (0, 0)][DBLP ] Information Hiding, 1999, pp:348-367 [Conf ] Farinaz Koushanfar , Gang Qu , Miodrag Potkonjak Intellectual Property Metering. [Citation Graph (0, 0)][DBLP ] Information Hiding, 2001, pp:81-95 [Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Fingerprinting Digital Circuits on Programmable Hardware. [Citation Graph (0, 0)][DBLP ] Information Hiding, 1998, pp:16-31 [Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Enhanced Intellectual Property Protection for Digital Circuits on Programmable Hardware. [Citation Graph (0, 0)][DBLP ] Information Hiding, 1999, pp:286-301 [Conf ] Boris Shimanovsky , Jessica Feng , Miodrag Potkonjak Hiding Data in DNA. [Citation Graph (0, 0)][DBLP ] Information Hiding, 2002, pp:373-386 [Conf ] Jennifer L. Wong , Darko Kirovski , Miodrag Potkonjak Computational Forensic Techniques for Intellectual Property Protection. [Citation Graph (0, 0)][DBLP ] Information Hiding, 2001, pp:66-80 [Conf ] Jennifer L. Wong , Miodrag Potkonjak Relative Generic Computational Forensic Techniques. [Citation Graph (0, 0)][DBLP ] Information Hiding, 2004, pp:148-163 [Conf ] Seapahn Meguerdichian , Farinaz Koushanfar , Miodrag Potkonjak , Mani B. Srivastava Coverage Problems in Wireless Ad-hoc Sensor Networks. [Citation Graph (0, 0)][DBLP ] INFOCOM, 2001, pp:1380-1387 [Conf ] Vladimir Bychkovskiy , Seapahn Megerian , Deborah Estrin , Miodrag Potkonjak A Collaborative Approach to In-Place Sensor Calibration. [Citation Graph (0, 0)][DBLP ] IPSN, 2003, pp:301-316 [Conf ] Alberto Cerpa , Jennifer L. Wong , Louane Kuang , Miodrag Potkonjak , Deborah Estrin Statistical model of lossy links in wireless sensor networks. [Citation Graph (0, 0)][DBLP ] IPSN, 2005, pp:81-88 [Conf ] Sasha Slijepcevic , Seapahn Megerian , Miodrag Potkonjak Characterization of Location Error in Wireless Sensor Networks: Analysis and Applications. [Citation Graph (0, 0)][DBLP ] IPSN, 2003, pp:593-608 [Conf ] Gang Qu , Darko Kirovski , Miodrag Potkonjak , Mani B. Srivastava Energy minimization of system pipelines using multiple voltages. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 1999, pp:362-365 [Conf ] Gang Qu , Miodrag Potkonjak Energy minimization with guaranteed quality of service. [Citation Graph (0, 0)][DBLP ] ISLPED, 2000, pp:43-49 [Conf ] Chunho Lee , Johnson Kin , Miodrag Potkonjak , William H. Mangione-Smith Designing power efficient hypermedia processors. [Citation Graph (0, 0)][DBLP ] ISLPED, 1999, pp:276-278 [Conf ] Farinaz Koushanfar , Abhijit Davare , Dai Tho Nguyen , Miodrag Potkonjak , Alberto L. Sangiovanni-Vincentelli Low power coordination in wireless ad-hoc networks. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:475-480 [Conf ] Gang Qu , Miodrag Potkonjak Achieving utility arbitrarily close to the optimal with limited energy. [Citation Graph (0, 0)][DBLP ] ISLPED, 2000, pp:125-130 [Conf ] Chunho Lee , Miodrag Potkonjak , Wayne Wolf System-Level Synthesis of Application Specific Systems using A* Search and Generalized Force-Directed Heuristics. [Citation Graph (0, 0)][DBLP ] ISSS, 1996, pp:2-7 [Conf ] Stephen Docy , Inki Hong , Miodrag Potkonjak Throughput Optimization in Disk-Based Real-Time Application Specific Systems. [Citation Graph (0, 0)][DBLP ] ISSS, 1996, pp:133-138 [Conf ] Gang Qu , Malena R. Mesarina , Miodrag Potkonjak System Synthesis of Synchronous Multimedia Applications. [Citation Graph (0, 0)][DBLP ] ISSS, 1999, pp:128-133 [Conf ] Sujit Dey , Miodrag Potkonjak Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs. [Citation Graph (0, 0)][DBLP ] ITC, 1994, pp:184-193 [Conf ] Jennifer L. Wong , Roozbeh Jafari , Miodrag Potkonjak Gateway Placement for Latency and Energy Efficient Data Aggregation. [Citation Graph (0, 0)][DBLP ] LCN, 2004, pp:490-497 [Conf ] Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems. [Citation Graph (0, 0)][DBLP ] MICRO, 1997, pp:330-335 [Conf ] James M. Burger , Christopher J. Cookson , Darko Kirovski , David Paul Maher , Miodrag Potkonjak , Jeremy Welt Multimedia copyright enforcement on the Internet (panel session). [Citation Graph (0, 0)][DBLP ] ACM Multimedia, 2000, pp:347-349 [Conf ] Seapahn Meguerdichian , Farinaz Koushanfar , Gang Qu , Miodrag Potkonjak Exposure in wireless Ad-Hoc sensor networks. [Citation Graph (0, 0)][DBLP ] MOBICOM, 2001, pp:139-150 [Conf ] Mani B. Srivastava , Richard R. Muntz , Miodrag Potkonjak Smart kindergarten: sensor-based wireless networks for smart developmental problem-solving enviroments. [Citation Graph (0, 0)][DBLP ] MOBICOM, 2001, pp:132-138 [Conf ] Alberto Cerpa , Jennifer L. Wong , Miodrag Potkonjak , Deborah Estrin Temporal properties of low power wireless links: modeling and implications on multi-hop routing. [Citation Graph (0, 0)][DBLP ] MobiHoc, 2005, pp:414-425 [Conf ] Seapahn Meguerdichian , Sasha Slijepcevic , Vahag Karayan , Miodrag Potkonjak Localized algorithms in wireless ad-hoc networks: location discovery and sensor exposure. [Citation Graph (0, 0)][DBLP ] MobiHoc, 2001, pp:106-116 [Conf ] Vasily G. Moshnyaga , Hoa Vo , Glenn Reinman , Miodrag Potkonjak Handheld System Energy Reduction by OS-Driven Refresh. [Citation Graph (0, 0)][DBLP ] PATMOS, 2006, pp:24-35 [Conf ] Inki Hong , Gang Qu , Miodrag Potkonjak , Mani B. Srivastava Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors. [Citation Graph (0, 0)][DBLP ] IEEE Real-Time Systems Symposium, 1998, pp:178-187 [Conf ] Milenko Drinic , Darko Kirovski , Miodrag Potkonjak Model-based compression in wireless ad hoc networks. [Citation Graph (0, 0)][DBLP ] SenSys, 2003, pp:231-242 [Conf ] Giacomino Veltri , Qingfeng Huang , Gang Qu , Miodrag Potkonjak Minimal and maximal exposure path algorithms for wireless embedded sensor networks. [Citation Graph (0, 0)][DBLP ] SenSys, 2003, pp:40-50 [Conf ] Ryan Kastner , Christina Hsieh , Miodrag Potkonjak , Majid Sarrafzadeh On the Sensitivity of Incremental Algorithms for Combinatorial Auctions. [Citation Graph (0, 0)][DBLP ] WECWIS, 2002, pp:81-88 [Conf ] Sasha Slijepcevic , Miodrag Potkonjak , Vlasios Tsiatsis , Scott Zimbeck , Mani B. Srivastava On Communication Security in Wireless Ad-Hoc Sensor Networks. [Citation Graph (0, 0)][DBLP ] WETICE, 2002, pp:139-144 [Conf ] Son Dao , Eddie C. Shek , Asha Vellaikal , Richard R. Muntz , Lixia Zhang , Miodrag Potkonjak , Ouri Wolfson Semantic Multicast: Intelligently Sharing Collaborative Sessions. [Citation Graph (0, 0)][DBLP ] ACM Comput. Surv., 1999, v:31, n:2es, pp:3- [Journal ] Jan M. Rabaey , C. Chu , P. Hoang , Miodrag Potkonjak Fast Prototyping of Datapath-Intensive Architectures. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 1991, v:8, n:2, pp:40-51 [Journal ] Inki Hong , Darko Kirovski , Kevin Kornegay , Miodrag Potkonjak High-level synthesis techniques for functional test pattern execution1. [Citation Graph (0, 0)][DBLP ] Integration, 1998, v:25, n:2, pp:161-180 [Journal ] Gang Qu , Naoyuki Kawabe , Kimiyoshi Usami , Miodrag Potkonjak Code Coverage-Based Power Estimation Techniques for Microprocessors. [Citation Graph (0, 0)][DBLP ] Journal of Circuits, Systems, and Computers, 2002, v:11, n:5, pp:557-0 [Journal ] Sasha Slijepcevic , Seapahn Megerian , Miodrag Potkonjak Location errors in wireless embedded sensor networks: sources, models, and effects on applications. [Citation Graph (0, 0)][DBLP ] Mobile Computing and Communications Review, 2002, v:6, n:3, pp:67-78 [Journal ] Ramesh Karri , Kyosun Kim , Miodrag Potkonjak Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2000, v:49, n:11, pp:1272-1284 [Journal ] Andrew E. Caldwell , Hyun-Jin Choi , Andrew B. Kahng , Stefanus Mantik , Miodrag Potkonjak , Gang Qu , Jennifer L. Wong Effective iterative techniques for fingerprinting design IP. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:208-215 [Journal ] Anantha P. Chandrakasan , Miodrag Potkonjak , Renu Mehra , Jan M. Rabaey , Robert W. Brodersen Optimizing power using transformations. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:12-31 [Journal ] Miguel R. Corazao , Marwan A. Khalaf , Lisa M. Guerra , Miodrag Potkonjak , Jan M. Rabaey Performance optimization using template mapping for datapath-intensive high-level synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:877-888 [Journal ] Sujit Dey , Vijay Gangaram , Miodrag Potkonjak A controller redesign technique to enhance testability of controller-data path circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:157-168 [Journal ] Sujit Dey , Miodrag Potkonjak Nonscan design-for-testability techniques using RT-level design information. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:12, pp:1488-1506 [Journal ] Inki Hong , Darko Kirovski , Gang Qu , Miodrag Potkonjak , Mani B. Srivastava Power optimization of variable-voltage core-based systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1702-1714 [Journal ] Andrew B. Kahng , John Lach , William H. Mangione-Smith , Stefanus Mantik , Igor L. Markov , Miodrag Potkonjak , Paul Tucker , Huijuan Wang , Gregory Wolfe Constraint-based watermarking techniques for design IP protection. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1236-1252 [Journal ] Kyosun Kim , Ramesh Karri , Miodrag Potkonjak Micropreemption synthesis: an enabling mechanism for multitask VLSI systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:19-30 [Journal ] Darko Kirovski , Milenko Drinic , Miodrag Potkonjak Engineering change protocols for behavioral and system synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1145-1155 [Journal ] Darko Kirovski , Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith Application-driven synthesis of memory-intensive systems-on-chip. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1316-1326 [Journal ] Darko Kirovski , Miodrag Potkonjak Local watermarks: methodology and application to behavioral synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1277-1283 [Journal ] Darko Kirovski , Miodrag Potkonjak , Lisa Guerra Improving the observability and controllability of datapaths foremulation-based debugging. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1529-1541 [Journal ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Fingerprinting techniques for field-programmable gate arrayintellectual property protection. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1253-1261 [Journal ] Farinaz Koushanfar , Darko Kirovski , Inki Hong , Miodrag Potkonjak , Marios C. Papaefthymiou Symbolic debugging of embedded hardware and software. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:392-401 [Journal ] Jan M. Rabaey , Miodrag Potkonjak Estimating implementation bounds for real time DSP application specific circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:669-683 [Journal ] Miodrag Potkonjak , Sujit Dey , Rabindra K. Roy Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:531-546 [Journal ] Miodrag Potkonjak , Sujit Dey , Rabindra K. Roy Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1141-1154 [Journal ] Miodrag Potkonjak , Jan M. Rabaey Maximally and arbitrarily fast implementation of linear andfeedback linear computations. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:30-43 [Journal ] Miodrag Potkonjak , Jan M. Rabaey Optimizing resource utilization using transformations. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:277-292 [Journal ] Miodrag Potkonjak , Jan M. Rabaey Algorithm selection: a quantitative optimization-intensive approach. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:524-532 [Journal ] Miodrag Potkonjak , Mani B. Srivastava Behavioral optimization using the manipulation of timing constraints. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:936-947 [Journal ] Miodrag Potkonjak , Mani B. Srivastava , Anantha P. Chandrakasan Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:151-165 [Journal ] Gregory Wolfe , Jennifer L. Wong , Miodrag Potkonjak Watermarking graph partitioning solutions. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1196-1204 [Journal ] Jennifer L. Wong , Azadeh Davoodi , Vishal Khandelwal , Ankur Srivastava , Miodrag Potkonjak A statistical methodology for wire-length prediction. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1327-1336 [Journal ] Jennifer L. Wong , Farinaz Koushanfar , Seapahn Megerian , Miodrag Potkonjak Probabilistic constructive optimization techniques. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:859-868 [Journal ] Jennifer L. Wong , Darko Kirovski , Miodrag Potkonjak Computational forensic techniques for intellectual property protection. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:987-994 [Journal ] Jennifer L. Wong , Rupak Majumdar , Miodrag Potkonjak Fair watermarking using combinatorial isolation lemmas. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:11, pp:1566-1574 [Journal ] Jennifer L. Wong , Miodrag Potkonjak , Sujit Dey Optimizing designs using the addition of deflection operations. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:50-59 [Journal ] Jennifer L. Wong , Gang Qu , Miodrag Potkonjak Optimization-intensive watermarking techniques for decision problems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:119-127 [Journal ] Gang Qu , Miodrag Potkonjak System synthesis of synchronous multimedia applications. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2003, v:2, n:1, pp:74-97 [Journal ] Seapahn Megerian , Farinaz Koushanfar , Miodrag Potkonjak , Mani B. Srivastava Worst and Best-Case Coverage in Sensor Networks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Mob. Comput., 2005, v:4, n:1, pp:84-92 [Journal ] Inki Hong , Miodrag Potkonjak , Ramesh Karri Power optimization using divide-and-conquer techniques for minimization of the number of operations. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:4, pp:405-429 [Journal ] Farinaz Koushanfar , Inki Hong , Miodrag Potkonjak Behavioral synthesis techniques for intellectual property protection. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:523-545 [Journal ] Kumar N. Lalgudi , Marios C. Papaefthymiou , Miodrag Potkonjak Optimizing computations for effective block-processing. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:604-630 [Journal ] Miodrag Potkonjak , Wayne Wolf A methodology and algorithms for the design of hard real-time multitasking ASICs. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:4, pp:430-459 [Journal ] Jennifer L. Wong , Gang Qu , Miodrag Potkonjak Power minimization in QoS sensitive systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:553-561 [Journal ] Seapahn Megerian , Farinaz Koushanfar , Gang Qu , Giacomino Veltri , Miodrag Potkonjak Exposure in Wireless Sensor Networks: Theory and Practical Solutions. [Citation Graph (0, 0)][DBLP ] Wireless Networks, 2002, v:8, n:5, pp:443-454 [Journal ] Gang Qu , Miodrag Potkonjak , Mile K. Stojcev Book review: Intellectual property protection in VLSI designs: Theory and practice, Hardcover, pp 183, plus XIX, Kluwer Academic Publishers, Boston, 2003, ISBN 1-4020-7320-8. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2004, v:44, n:4, pp:705-706 [Journal ] Farinaz Koushanfar , Miodrag Potkonjak CAD-based Security, Cryptography, and Digital Rights Management. [Citation Graph (0, 0)][DBLP ] DAC, 2007, pp:268-269 [Conf ] Jessica Feng , Lewis Girod , Miodrag Potkonjak Location Discovery Using Data-Driven Statistical Error Modeling. [Citation Graph (0, 0)][DBLP ] INFOCOM, 2006, pp:- [Conf ] Farinaz Koushanfar , Nina Taft , Miodrag Potkonjak Sleeping Coordination for Comprehensive Sensing Using Isotonic Regression and Domatic Partitions. [Citation Graph (0, 0)][DBLP ] INFOCOM, 2006, pp:- [Conf ] Vasily G. Moshnyaga , Hua Vo , Glenn Reinman , Miodrag Potkonjak Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:2108-2111 [Conf ] Foad Dabiri , Ani Nahapetian , Miodrag Potkonjak , Majid Sarrafzadeh Soft Error-Aware Power Optimization Using Gate Sizing. [Citation Graph (0, 0)][DBLP ] PATMOS, 2007, pp:255-267 [Conf ] Ani Nahapetian , Foad Dabiri , Miodrag Potkonjak , Majid Sarrafzadeh Optimization for Real-Time Systems with Non-convex Power Versus Speed Models. [Citation Graph (0, 0)][DBLP ] PATMOS, 2007, pp:443-452 [Conf ] Farinaz Koushanfar , Abhijit Davare , David T. Nguyen , Alberto L. Sangiovanni-Vincentelli , Miodrag Potkonjak Techniques for maintaining connectivity in wireless ad-hoc networks under energy constraints. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2007, v:6, n:3, pp:- [Journal ] Inki Hong , Miodrag Potkonjak , Ramesh Karri A heterogeneous built-in self-repair approach using system-level synthesis flexibility. [Citation Graph (0, 0)][DBLP ] IEEE Transactions on Reliability, 2004, v:53, n:1, pp:93-101 [Journal ] Mani B. Srivastava , Miodrag Potkonjak Optimum and heuristic transformation techniques for simultaneous optimization of latency and throughput. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:2-19 [Journal ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Low overhead fault-tolerant FPGA systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:212-221 [Journal ] Lisa M. Guerra , Miodrag Potkonjak , Jan M. Rabaey Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:158-167 [Journal ] N. R. Shnidman , William H. Mangione-Smith , Miodrag Potkonjak On-line fault detection for bus-based field programmable gate arrays. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:656-666 [Journal ] Darko Kirovski , Miodrag Potkonjak , Lisa M. Guerra Cut-based functional debugging for programmable systems-on-chip. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:40-51 [Journal ] Johnson Kin , Chunho Lee , William H. Mangione-Smith , Miodrag Potkonjak Exploring the diversity of multimedia systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2001, v:9, n:3, pp:474-485 [Journal ] Gang Qu , Miodrag Potkonjak Techniques for energy-efficient communication pipeline design. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:542-549 [Journal ] Scheduling with integer time budgeting for low-power optimization. [Citation Graph (, )][DBLP ] Energy Balancing Routing Schemes for Low-Power Wireless Networks. [Citation Graph (, )][DBLP ] Localized Probabilistic Routing for Data Gathering in Wireless Ad Hoc Networks. [Citation Graph (, )][DBLP ] (Bio)-behavioral CAD. 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