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Publications of Author

1. Ivo Schanstra, A. J. van de Goor
   Consequences of RAM Bitline Twisting for Test Coverage. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:11176-11177 [Conf]
   
2. A. J. van de Goor, Ivo Schanstra
   Address and Data Scrambling: Causes and Impact on Memory Tests. [Citation Graph (0, 0)][DBLP]
   DELTA, 2002, pp:128-136 [Conf]
   
3. A. J. van de Goor, Yervant Zorian, Ivo Schanstra
   Functional Tests for Ring-Address SRAM-type FIFOs. [Citation Graph (0, 0)][DBLP]
   EDAC-ETC-EUROASIC, 1994, pp:666- [Conf]
   
4. A. J. van de Goor, Ivo Schanstra
   Industrial evaluation of stress combinations for march tests applied to SRAMs. [Citation Graph (0, 0)][DBLP]
   ITC, 1999, pp:983-992 [Conf]
   
5. Ivo Schanstra, Dharmajaya Lukita, A. J. van de Goor, Kees Veelenturf, Paul J. van Wijnen
   Semiconductor manufacturing process monitoring using built-in self-test for embedded memories. [Citation Graph (0, 0)][DBLP]
   ITC, 1998, pp:872-0 [Conf]
   
6. Yervant Zorian, A. J. van de Goor, Ivo Schanstra
   An Effective BIST Scheme for Ring-Address Type FIFOs. [Citation Graph (0, 0)][DBLP]
   ITC, 1994, pp:378-387 [Conf]
   
7. Zaid Al-Ars, Martin Herzog, Ivo Schanstra, A. J. van de Goor
   Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. [Citation Graph (0, 0)][DBLP]
   MTDT, 2004, pp:32-37 [Conf]