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Publications of Author

1. Jim Torresen, Thor Arne Lovland
   Parts Obsolescence Challenges for the Electronics Industry. [Citation Graph (0, 0)][DBLP]
   DDECS, 2007, pp:131-134 [Conf]
   
2. Jim Torresen, Jorgen Norendal, Kyrre Glette
   Establishing a New Course in Reconfigurable Logic System Design. [Citation Graph (0, 0)][DBLP]
   DDECS, 2007, pp:227-230 [Conf]
   
3. Jim Torresen
   Scalable Evolvable Hardware Applied to Road Image Recognition. [Citation Graph (0, 0)][DBLP]
   Evolvable Hardware, 2000, pp:245-252 [Conf]
   
4. Jim Torresen
   Exploring Knowledge Schemes for Efficient Evolution of Hardware. [Citation Graph (0, 0)][DBLP]
   Evolvable Hardware, 2004, pp:209-216 [Conf]
   
5. Knut Arne Vinger, Jim Torresen
   Implementing Evolution of FIR-Filters Efficiently in an FPGA. [Citation Graph (0, 0)][DBLP]
   Evolvable Hardware, 2003, pp:26-32 [Conf]
   
6. Lukás Sekanina, Jim Torresen
   Detection of Norwegian Speed Limit Signs. [Citation Graph (0, 0)][DBLP]
   ESM, 2002, pp:337-340 [Conf]
   
7. Jim Torresen
   Evolving both Hardware Subsystems and the Selection of Variants of such into an Assembled System. [Citation Graph (0, 0)][DBLP]
   ESM, 2002, pp:451-457 [Conf]
   
8. Jim Torresen, Vidar Engh Skangen
   A Signal Processing Architecture Based on RAM Technology. [Citation Graph (0, 0)][DBLP]
   ESM, 2002, pp:317-319 [Conf]
   
9. Jim Torresen, Knut Arne Vinger
   High Performance Computing by Context Switching Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
   ESM, 2002, pp:207-210 [Conf]
   
10. Jim Torresen
    A Dynamic Fitness Function Applied to Improve the Generalisation when Evolving a Signal Processing Hardware Architecture. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2002, pp:267-279 [Conf]
    
11. Shaomeng Li, Jim Torresen, Oddvar Søråsen
    Exploiting Reconfigurable Hardware for Network Security. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:292-293 [Conf]
    
12. Shaomeng Li, Jim Torresen, Oddvar Søråsen
    Exploiting Stateful Inspection of Network Security in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1153-1157 [Conf]
    
13. Jim Torresen
    Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:230-239 [Conf]
    
14. Jim Torresen
    An Evolvable Hardware Tutorial. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:821-830 [Conf]
    
15. Kyrre Glette, Jim Torresen
    A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device. [Citation Graph (0, 0)][DBLP]
    ICES, 2005, pp:66-75 [Conf]
    
16. Jim Torresen
    Two-Step Incremental Evolution of a Prosthetic Hand Controller Based on Digital Logic Gates. [Citation Graph (0, 0)][DBLP]
    ICES, 2001, pp:1-13 [Conf]
    
17. Jim Torresen
    Evolving Multiplier Circuits by Training Set and Training Vector Partitioning. [Citation Graph (0, 0)][DBLP]
    ICES, 2003, pp:228-237 [Conf]
    
18. Jim Torresen
    A Divide-and-Conquer Approach to Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1998, pp:57-65 [Conf]
    
19. Jim Torresen, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita, Olav Landsverk
    Exploiting Parallel Computers to Reduce Neural Network Training Time of Real Applications. [Citation Graph (0, 0)][DBLP]
    ISHPC, 1997, pp:405-414 [Conf]
    
20. Jim Torresen, Jorgen W. Bakke, Lukás Sekanina
    Recognizing Speed Limit Sign Numbers by Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    PPSN, 2004, pp:682-691 [Conf]
    
21. Jim Torresen, Jonas Jakobsen
    An FPGA Implemented Processor Architecture with Adaptive Resolution. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:386-389 [Conf]
    
22. Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yoshiki Yamaguchi
    On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:373-380 [Conf]
    
23. Jim Torresen
    A Scalable Approach to Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    Genetic Programming and Evolvable Machines, 2002, v:3, n:3, pp:259-282 [Journal]
    
24. Jim Torresen
    The Convergence of Backpropagation Trained Neural Networks for Various Weight Update Frequencies. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 1997, v:8, n:3, pp:263-277 [Journal]
    
25. Kyrre Glette, Jim Torresen, Moritoshi Yasunaga
    An Online EHW Pattern Recognition System Applied to Face Image Recognition. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2007, pp:271-280 [Conf]
    
26. Jim Torresen, Kyrre Glette
    Improving Flexibility in On-Line Evolvable Systems by Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ICES, 2007, pp:391-402 [Conf]
    
27. Kyrre Glette, Jim Torresen, Moritoshi Yasunaga
    An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification. [Citation Graph (0, 0)][DBLP]
    ICES, 2007, pp:1-12 [Conf]
    
28. 
    An Indirect Approach to the Three-Dimensional Multi-pipe Routing Problem. [Citation Graph (, )][DBLP]
    
    
29. 
    Evolutionary Approaches to the Three-dimensional Multi-pipe Routing Problem: A Comparative Study Using Direct Encodings. [Citation Graph (, )][DBLP]
    
    
30. 
    Scalability, generalization and coevolution -- experimental comparisons applied to automated facility layout planning. [Citation Graph (, )][DBLP]
    
    
31. 
    A Comparison of Evolvable Hardware Architectures for Classification Tasks. [Citation Graph (, )][DBLP]
    
    
32. 
    Indirect Online Evolution - A Conceptual Framework for Adaptation in Industrial Robotic Systems. [Citation Graph (, )][DBLP]
    
    
33. 
    Adaptive Facial Behaviour using Selected Machine Learning Methods. [Citation Graph (, )][DBLP]
    
    
34. 
    Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA. [Citation Graph (, )][DBLP]
    
    
35. 
    Coevolving heuristics for the Distributor's Pallet Packing Problem. [Citation Graph (, )][DBLP]
    
    
36. 
    Making Hardware Soft in Intelligent Systems. [Citation Graph (, )][DBLP]