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D. N. Jayasimha: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David R. Lutz, D. N. Jayasimha
    The Half-Adder Form and Early Branch Condition Resolution. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1997, pp:266-273 [Conf]
  2. Nachum Dershowitz, D. N. Jayasimha, Seungjoon Park
    Bounded Fairness. [Citation Graph (0, 0)][DBLP]
    Verification: Theory and Practice, 2003, pp:304-317 [Conf]
  3. David R. Lutz, D. N. Jayasimha
    Early Zero Detection. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:545-0 [Conf]
  4. D. N. Jayasimha
    Parallel Access to Synchronization Variables. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:97-100 [Conf]
  5. D. N. Jayasimha
    Distributed Synchronizers. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:23-27 [Conf]
  6. Jeff D. Martens, D. N. Jayasimha
    Compiling for Hierarchical Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:107-110 [Conf]
  7. Jeff D. Martens, D. N. Jayasimha
    A Tree Structured Hierarchical Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:561-562 [Conf]
  8. N. S. Sundar, D. N. Jayasimha, Dhabaleswar K. Panda, P. Sadayappan
    Hybrid Algorithms for Complete Exchange in 2D Meshes. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1996, pp:181-188 [Conf]
  9. D. N. Jayasimha, Jeff D. Martens
    Some Architectural and Compilation Issues in the Design of Hierarchical Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:567-572 [Conf]
  10. Loren Schwiebert, D. N. Jayasimha
    Mapping to Reduce Contention in Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:248-253 [Conf]
  11. D. N. Jayasimha, M. E. Hayder, S. K. Pillay
    Parallelizing Navier-Stokes Computations on a Variety of Architectural Platforms. [Citation Graph (0, 0)][DBLP]
    SC, 1995, pp:- [Conf]
  12. Loren Schwiebert, D. N. Jayasimha
    Optimal fully adaptive wormhole routing for meshes. [Citation Graph (0, 0)][DBLP]
    SC, 1993, pp:782-791 [Conf]
  13. Loren Schwiebert, D. N. Jayasimha
    A Universal Proof Technique for Deadlock-Free Routing in Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    SPAA, 1995, pp:175-184 [Conf]
  14. D. N. Jayasimha
    Fault Tolerance in a Multisensor Environment. [Citation Graph (0, 0)][DBLP]
    Symposium on Reliable Distributed Systems, 1994, pp:2-11 [Conf]
  15. D. N. Jayasimha, Loren Schwiebert, D. Manivannan, Jeff A. May
    A foundation for designing deadlock-free routing algorithms in wormhole networks. [Citation Graph (0, 0)][DBLP]
    J. ACM, 2003, v:50, n:2, pp:250-275 [Journal]
  16. Loren Schwiebert, D. N. Jayasimha
    A Necessary and Sufficient Condition for Deadlock-Free Wormhole Routing. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:32, n:1, pp:103-117 [Journal]
  17. Loren Schwiebert, D. N. Jayasimha
    Optimal Fully Adaptive Minimal Wormhole Routing for Meshes. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:27, n:1, pp:56-70 [Journal]
  18. David R. Lutz, D. N. Jayasimha
    Do Fixed-Processor Communication-Time Tradeoffs Exist? [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1995, v:5, n:, pp:311-320 [Journal]
  19. S. Sitharama Iyengar, D. N. Jayasimha, D. Nadig
    A Versatile Architecture for the Distributed Sensor Integration Problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:2, pp:175-185 [Journal]
  20. D. N. Jayasimha, M. E. Hayder, S. K. Pillay
    An Evaluation of Architectural Platforms for Parallel Navier-Stokes Computations. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 1997, v:11, n:1, pp:41-60 [Journal]
  21. N. S. Sundar, D. N. Jayasimha, Dhabaleswar K. Panda
    Hybrid Algorithms for Complete Exchange in 2D Meshes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:12, pp:1201-1218 [Journal]
  22. John D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh
    Research Challenges for On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:96-108 [Journal]

  23. What is an effective schedule? [Citation Graph (, )][DBLP]


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