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Stephen W. Keckler: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jaehyuk Huh, Doug Burger, Stephen W. Keckler
    Exploring the Design Space of Future CMPs. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:199-210 [Conf]
  2. Ramadass Nagarajan, Sundeep K. Kushwaha, Doug Burger, Kathryn S. McKinley, Calvin Lin, Stephen W. Keckler
    Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:74-84 [Conf]
  3. Nicholas P. Carter, Stephen W. Keckler, William J. Dally
    Hardware Support for Fast Capability-based Addressing. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:319-327 [Conf]
  4. Changkyu Kim, Doug Burger, Stephen W. Keckler
    An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:211-222 [Conf]
  5. Rajagopalan Desikan, Simha Sethumadhavan, Doug Burger, Stephen W. Keckler
    Scalable selective re-execution for EDGE architectures. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:120-132 [Conf]
  6. Premkishore Shivakumar, Michael Kistler, Stephen W. Keckler, Doug Burger, Lorenzo Alvisi
    Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic. [Citation Graph (0, 0)][DBLP]
    DSN, 2002, pp:389-398 [Conf]
  7. Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger
    Static Energy Reduction Techniques for Microprocessor Caches. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:276-283 [Conf]
  8. Karthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, Doug Burger
    Routed Inter-ALU Networks for ILP Scalability and Performance. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:170-0 [Conf]
  9. Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger
    Exploiting Microarchitectural Redundancy For Defect Tolerance. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:481-488 [Conf]
  10. Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler
    A NUCA substrate for flexible CMP cache sharing. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:31-40 [Conf]
  11. Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger
    Clock rate versus IPC: the end of the road for conventional microarchitectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:248-259 [Conf]
  12. M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas
    The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:14-24 [Conf]
  13. Stephen W. Keckler, William J. Dally
    Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:202-213 [Conf]
  14. Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee
    Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:306-317 [Conf]
  15. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
    Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:422-433 [Conf]
  16. Nicholas P. Carter, William J. Dally, Whay Sing Lee, Stephen W. Keckler, Andrew Chang
    Processor Mechanisms for Software Shared Memory. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2000, pp:120-133 [Conf]
  17. Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger
    Microprocessor pipeline energy analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:282-287 [Conf]
  18. Kartik K. Agaram, Stephen W. Keckler, Calvin Lin, Kathryn S. McKinley
    Decomposing memory performance: data structures and phases. [Citation Graph (0, 0)][DBLP]
    ISMM, 2006, pp:95-103 [Conf]
  19. Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee
    The M-Machine multicomputer. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:146-156 [Conf]
  20. Daniel A. Jiménez, Stephen W. Keckler, Calvin Lin
    The impact of delay on the design of branch predictors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:67-76 [Conf]
  21. Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler
    A design space evaluation of grid processor architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:40-51 [Conf]
  22. Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, Doug Burger
    Universal Mechanisms for Data-Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:303-314 [Conf]
  23. Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
    Scalable Hardware Memory Disambiguation for High ILP Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:399-410 [Conf]
  24. Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley
    Dataflow Predication. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:89-102 [Conf]
  25. Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger
    Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:480-491 [Conf]
  26. Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Michael Dahlin, Lizy Kurian John, Calvin Lin, Charles R. Moore, James H. Burrill, Robert G. McDonald, William Yode
    Scaling to the End of Silicon with EDGE Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:7, pp:44-55 [Journal]
  27. Whay Sing Lee, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Andrew Chang
    An Efficient, Protected Message Interface. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:11, pp:69-75 [Journal]
  28. Changkyu Kim, Doug Burger, Stephen W. Keckler
    Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:99-107 [Journal]
  29. Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
    Scalable Hardware Memory Disambiguation for High-ILP Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:118-127 [Journal]
  30. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
    Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:46-51 [Journal]
  31. Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, Llorenc Cruz, Fernando Latorre, Antonio González, Mateo Valero
    Errata on "Measuring Experimental Error in Microprocessor Simulation". [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2002, v:30, n:1, pp:2-4 [Journal]
  32. Doug Burger, Todd M. Austin, Stephen W. Keckler
    Recent extensions to the SimpleScalar tool suite. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS Performance Evaluation Review, 2004, v:31, n:4, pp:4-7 [Journal]
  33. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore
    TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:1, pp:62-93 [Journal]
  34. Stephen W. Keckler, Andrew Chang, Whay Sing Lee, Sandeep Chatterjee, William J. Dally
    Concurrent Event Handling through Multithreading. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:9, pp:903-916 [Journal]
  35. Heather Hanson, Stephen W. Keckler, Karthick Rajamani, Soraya Ghiasi, Freeman L. Rawson III, Juan Rubio
    Power, Performance, and Thermal Management for High-Performance Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  36. Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler
    Late-binding: enabling unordered load-store queues. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:347-357 [Conf]
  37. Jayaram Mudigonda, Harrick M. Vin, Stephen W. Keckler
    Reconciling performance and programmability in networking systems. [Citation Graph (0, 0)][DBLP]
    SIGCOMM, 2007, pp:73-84 [Conf]
  38. Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger
    Implementation and Evaluation of a Dynamically Routed Processor Operand Network. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:7-17 [Conf]
  39. John D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh
    Research Challenges for On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:96-108 [Journal]
  40. Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger
    On-Chip Interconnection Networks of the TRIPS Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:41-50 [Journal]
  41. Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler
    A NUCA Substrate for Flexible CMP Cache Sharing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1028-1040 [Journal]
  42. Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger
    Static energy reduction techniques for microprocessor caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:303-313 [Journal]

  43. Multitasking workload scheduling on flexible-core chip multiprocessors. [Citation Graph (, )][DBLP]


  44. An evaluation of the TRIPS computer system. [Citation Graph (, )][DBLP]


  45. The future of multi-core technologies. [Citation Graph (, )][DBLP]


  46. Regional congestion awareness for load balance in networks-on-chip. [Citation Graph (, )][DBLP]


  47. Express Cube Topologies for on-Chip Interconnects. [Citation Graph (, )][DBLP]


  48. Design and Implementation of the TRIPS Primary Memory System. [Citation Graph (, )][DBLP]


  49. Implementation and Evaluation of On-Chip Network Architectures. [Citation Graph (, )][DBLP]


  50. Counting Dependence Predictors. [Citation Graph (, )][DBLP]


  51. Thermal response to DVFS: analysis with an Intel Pentium M. [Citation Graph (, )][DBLP]


  52. End-to-end validation of architectural power models. [Citation Graph (, )][DBLP]


  53. Critical path analysis of the TRIPS architecture. [Citation Graph (, )][DBLP]


  54. Analysis of the TRIPS prototype block predictor. [Citation Graph (, )][DBLP]


  55. Composable Lightweight Processors. [Citation Graph (, )][DBLP]


  56. Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip. [Citation Graph (, )][DBLP]


  57. High performance dense linear algebra on a spatially distributed processor. [Citation Graph (, )][DBLP]


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