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Publications of Author

1. Noureddine Chabini, Wayne Wolf
   An approach for reducing dynamic power consumption in synchronous sequential digital designs. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:198-204 [Conf]
   
2. Noureddine Chabini, Wayne Wolf
   Minimizing Variables' Lifetime in Loop-Intensive Applications. [Citation Graph (0, 0)][DBLP]
   EMSOFT, 2003, pp:100-116 [Conf]
   
3. Noureddine Chabini, Wayne Wolf
   An approach for integrating basic retiming and software pipelining. [Citation Graph (0, 0)][DBLP]
   EMSOFT, 2004, pp:287-296 [Conf]
   
4. Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria
   Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2003, pp:221-224 [Conf]
   
5. Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria
   Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages. [Citation Graph (0, 0)][DBLP]
   ICCD, 2001, pp:546-552 [Conf]
   
6. Noureddine Chabini, Yvon Savaria
   Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques. [Citation Graph (0, 0)][DBLP]
   ISSS, 2001, pp:209-214 [Conf]
   
7. Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria
   Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:346-351 [Journal]
   
8. Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria
   Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:187-204 [Journal]
   
9. Noureddine Chabini, Wayne Wolf
   Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:573-589 [Journal]
   
10. Noureddine Chabini, Wayne Wolf
    Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1113-1126 [Journal]
    
11. Noureddine Chabini
    A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:64-74 [Conf]
    
12. Noureddine Chabini, Wayne Wolf
    Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:255-268 [Conf]
    
13. 
    An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers. [Citation Graph (, )][DBLP]
    
    
14. 
    FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. [Citation Graph (, )][DBLP]
    
    
15. 
    Register binding guided by the size of variables. [Citation Graph (, )][DBLP]