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Jaewon Seo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jaewon Seo, Nikil D. Dutt
    A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:836-841 [Conf]
  2. Jaewon Seo, Taewhan Kim, Ki-Seok Chung
    Profile-based optimal intra-task voltage scheduling for hard real-time applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:87-92 [Conf]
  3. Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
    An integrated algorithm for memory allocation and assignment in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:608-611 [Conf]
  4. Jaewon Seo, Taewhan Kim, Nikil D. Dutt
    Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:450-455 [Conf]
  5. Jaewon Seo, Sunggu Lee, Jong Kim
    Synchronous Load Balancing in Hypercube Multicomputers with Faulty Nodes. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1997, pp:414-421 [Conf]
  6. Jaewon Seo, Taewhan Kim
    Memory exploration utilizing scheduling effects in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:73-76 [Conf]
  7. Kyungwan Nam, Jaewon Seo, Sunggu Lee, Jong Kim
    Synchronous Load Balancing in Hypercube Multicomputers with Faulty Nodes. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1999, v:58, n:1, pp:26-43 [Journal]
  8. Jaewon Seo, Taewhan Kim, Joonwon Lee
    Optimal intratask dynamic voltage-scaling technique and its practical extensions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:47-57 [Journal]
  9. Mihui Kim, Jaewon Seo, Kijoon Chae
    Integrated Notification Architecture Based on Overlay Against DDoS Attacks on Convergence Network. [Citation Graph (0, 0)][DBLP]
    SEUS, 2007, pp:466-476 [Conf]
  10. Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
    Memory allocation and mapping in high-level synthesis - an integrated approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:928-938 [Journal]

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