Conferences in DBLP
C. K. Cheng , Steve Lin , Andrew B. Kahng , Keh-Jeng Chang , Vijay Pitchumani , Toshiyuki Shibuya , Roberto Suaya , Zhiping Yu , Fook-Luen Heng , Don MacMillen Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Madhavan Silicon compilation: the answer to reducing IC development costs. [Citation Graph (0, 0)][DBLP ] Conf ] Jan M. Rabaey Design at the end of the silicon roadmap. [Citation Graph (0, 0)][DBLP ] Conf ] David Blaauw , Anirudh Devgan , Farid N. Najm Leakage power: trends, analysis and avoidance. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Tony Ma , Ivo Bolsens , Phil Moorby , Jan M. Rabaey , John Sanguinetti , Kazutoshi Wakabayashi , Yoshi Watanabe Are we ready for system-level synthesis? [Citation Graph (0, 0)][DBLP ] Conf ] David Chen , Nancy Wu , Wayne Dai , Jun Tan , Weiping Liu , Hao Min , Jian-yue Pan Panel III: EDA market in China. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Pitchumani Embedded tutorial I: design for manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenghua Jiang The development of integrated circuit industry in China. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Grundmann Challenges to covering the high-level to silicon gap. [Citation Graph (0, 0)][DBLP ] Conf ] Yin Wang , Xianlong Hong , Tong Jing , Yang Yang , Xiaodong Hu , Guiying Yan The polygonal contraction heuristic for rectilinear Steiner tree construction. [Citation Graph (0, 0)][DBLP ] Conf ] Hongxia Wang , Samuel Rodríguez , Cagdas Dirik , Amol Gole , Vincent Chan , Bruce Jacob TERPS: the embedded reliable processing system. [Citation Graph (0, 0)][DBLP ] Conf ] Narayanan Vijaykrishnan , Yuan Xie , Mary Jane Irwin Designing reliable circuit in the presence of soft errors. [Citation Graph (0, 0)][DBLP ] Conf ] Todd M. Austin , Valeria Bertacco , David Blaauw , Trevor N. Mudge Opportunities and challenges for better than worst-case design. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios Soudris , Spiridon Nikolaidis , S. Siskos , Konstantinos Tatas , K. Siozios , G. Koutroumpezis , Nikolaos Vassiliadis , V. Kalenteridis , H. Pournara , I. Pappas , Adonios Thanailakis AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. [Citation Graph (0, 0)][DBLP ] Conf ] Hongyan Jian , Zhangwen Tang , Jie He , Jinglan He , Min Hao Standard CMOS technology on-chip inductors with pn junctions substrate isolation. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Hu , Tong Jing , Xianlong Hong , Zhe Feng 0002 , Xiaodong Hu , Guiying Yan An-OARSMan: obstacle-avoiding routing tree construction with good length performance. [Citation Graph (0, 0)][DBLP ] Conf ] Hao-Yun Chin , Chao-Chung Cheng , Yu-Kun Lin , Tian-Sheuan Chang A bandwidth efficient subsampling-based block matching architecture for motion estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Jagannathan , Hannah Honghua Yang , Kris Konigsfeld , Dan Milliron , Mosur Mohan , Michail Romesis , Glenn Reinman , Jason Cong Microarchitecture evaluation with floorplanning and interconnect pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Akinori Shinmyo , Masanori Hashimoto , Hidetoshi Onodera Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. [Citation Graph (0, 0)][DBLP ] Conf ] Chi Huang , Xinyu Wu , Jinmei Lai , Chengshou Sun , Gang Li A design of high speed double precision floating point adder using macro modules. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Morimoto , Osamu Kiriyama , Hidekazu Adachi , Zhaomin Zhu , Tetsushi Koide , Hans Jürgen Mattausch A low-power video segmentation LSI with boundary-active-only architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Zhuo Li , Cliff C. N. Sze , Charles J. Alpert , Jiang Hu , Weiping Shi Making fast buffer insertion even faster via approximation techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Xu Ningyi , Li Shaohua , Yu Wei , He Guanghui , Zhang Hao , Luo Fei , Zhou Zucheng The design and implementation of a DVB receiving chip with PCI interface. [Citation Graph (0, 0)][DBLP ] Conf ] Dehui Zhang , Quan Liang Zhao , Jun Gang Han Design and implementation of an SDH high-speed switch. [Citation Graph (0, 0)][DBLP ] Conf ] Zhong-Ching Lu , Ting-Chi Wang Concurrent flip-flop and buffer insertion with adaptive blockage avoidance. [Citation Graph (0, 0)][DBLP ] Conf ] Arias Tanti Hapsari , Eniman Y. Syamsudin , Imron Pramana Design of vehicle position tracking system using short message services and its implementation on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Wang , Jianyu Zhang , Xuan Wang , Jinmei Lai , Chengshou Sun Design of A 2.4-GHz integrated frequency synthesizer. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Jianhua , Long Jieyi , Xu Wenhua , Ye Hongfei An improved test access mechanism structure and optimization technique in system-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Tianpei Zhang , Sachin S. Sapatnekar Buffering global interconnects in structured ASIC design. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivasan Murali , Luca Benini , Giovanni De Micheli Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. [Citation Graph (0, 0)][DBLP ] Conf ] César A. M. Marcon , André Borin Suarez , Altamiro Amadeu Susin , Luigi Carro , Flávio Rech Wagner Time and energy efficient mapping of embedded applications onto NoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Liang-Yu Lin , Cheng-Yeh Wang , Pao-Jui Huang , Chih-Chieh Chou , Jing-Yang Jou Communication-driven task binding for multiprocessor with latency insensitive network-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Gerstlauer , Dongwan Shin , Rainer Dömer , Daniel D. Gajski System-level communication modeling for network-on-chip synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Luciano Ost , Aline Mello , José Palma , Fernando Gehm Moraes , Ney Calazans MAIA: a framework for networks on chip generation and verification. [Citation Graph (0, 0)][DBLP ] Conf ] Yinhe Han , Yu Hu , Huawei Li , Xiaowei Li Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. [Citation Graph (0, 0)][DBLP ] Conf ] Yasumi Doi , Seiji Kajihara , Xiaoqing Wen , Lei Li , Krishnendu Chakrabarty Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Fu Li Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Shi , Yiorgos Makris SPIN-PAC: test compaction for speed-independent circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michihiro Shintani , Toshihiro Ohara , Hideyuki Ichihara , Tomoo Inoue A Huffman-based coding with efficient test application. [Citation Graph (0, 0)][DBLP ] Conf ] Rouying Zhan , Haolu Xie , Haigang Feng , Albert Z. Wang ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaolang Yan , Ye Chen , Zheng Shi , Yue Ma A new method for model based frugal OPC. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Zhan , Sachin S. Sapatnekar Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up. [Citation Graph (0, 0)][DBLP ] Conf ] Yi Zou , Qiang Zhou , Yici Cai , Xianlong Hong , Sheldon X.-D. Tan Analysis of buffered hybrid structured clock networks. [Citation Graph (0, 0)][DBLP ] Conf ] Liang Huang , Yici Cai , Qiang Zhou , Xianlong Hong , Jiang Hu , Yongqiang Lu Clock network minimization methodology based on incremental placement. [Citation Graph (0, 0)][DBLP ] Conf ] Hongyu Chen , Chung-Kuan Cheng A multi-level transmission line network approach for multi-giga hertz clock distribution. [Citation Graph (0, 0)][DBLP ] Conf ] Zhixin Tian , Huazhong Yang , Rong Luo Gibbs sampling in power grid analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Yu , Lei He , Zhenyu Qi , Sheldon X.-D. Tan A wideband hierarchical circuit reduction for massively coupled interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Tong Jing , Ling Zhang , Jinghong Liang , Jingyu Xu , Xianlong Hong , Jinjun Xiong , Lei He A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yan Zhang Thermal-driven multilevel routing for 3-D ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Lizheng Zhang , Yuhen Hu , Charlie Chung-Ping Chen Wave-pipelined on-chip global interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Junpei Inoue , Hiroyuki Ito , Shinichiro Gomi , Takanori Kyogoku , Takumi Uezono , Kenichi Okada , Kazuya Masu Evaluation of on-chip transmission line interconnect using wire length distribution. [Citation Graph (0, 0)][DBLP ] Conf ] Samar Abdi , Daniel Gajski A formalism for functionality preserving system level transformations. [Citation Graph (0, 0)][DBLP ] Conf ] KiSeun Kwon , Youngmin Yi , Dohyung Kim , Soonhoi Ha Embedded software generation from system level specification for multi-tasking embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Youngchul Cho , Sungjoo Yoo , Kiyoung Choi , Nacer-Eddine Zergainoh , Ahmed Amine Jerraya Scheduler implementation in MP SoC design. [Citation Graph (0, 0)][DBLP ] Conf ] G. Chen , Mahmut T. Kandemir Optimizing embedded applications using programmer-inserted hints. [Citation Graph (0, 0)][DBLP ] Conf ] Dohyung Kim , Soonhoi Ha Static analysis and automatic code synthesis of flexible FSM model. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Chieh Lin , Feng Lu , Kai Yang , Kwang-Ting Cheng Constraint extraction for pseudo-functional scan-based delay testing. [Citation Graph (0, 0)][DBLP ] Conf ] Hafizur Rahaman , Debesh K. Das Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. [Citation Graph (0, 0)][DBLP ] Conf ] Xijiang Lin , Janusz Rajski Propagation delay fault: a new fault model to test delay faults. [Citation Graph (0, 0)][DBLP ] Conf ] Katherine Shu-Min Li , Chung-Len Lee , Chauchin Su , Jwu E. Chen Oscillation ring based interconnect test scheme for SOC. [Citation Graph (0, 0)][DBLP ] Conf ] Junhao Shi , Görschwin Fey , Rolf Drechsler Bridging fault testability of BDD circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Debjit Sinha , Hai Zhou Yield driven gate sizing for coupling-noise reduction under uncertainty. [Citation Graph (0, 0)][DBLP ] Conf ] Yun-Ru Wu , Ming-Chao Tsai , Ting-Chi Wang Maze routing with OPC consideration. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Murakawa , Mitiko Miura-Mattausch , Tetsuya Higuchi Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Xiren Wang , Wenjian Yu , Zeyi Wang Substrate resistance extraction with direct boundary element method. [Citation Graph (0, 0)][DBLP ] Conf ] Vineet Agarwal , Navneeth Kankani , Ravishankar Rao , Sarvesh Bhardwaj , Janet Wang An efficient combinationality check technique for the synthesis of cyclic combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ke Cao , Puneet Dhawan , Jiang Hu Library cell layout with Alt-PSM compliance and composability. [Citation Graph (0, 0)][DBLP ] Conf ] Rasit Onur Topaloglu , Alex Orailoglu Forward discrete probability propagation method for device performance characterization under process variations. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenyu Qi , Sheldon X.-D. Tan , Hao Yu , Lei He Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Huiying Yang , Mukesh Ranjan , Wim Verhaegen , Mengmeng Ding , Ranga Vemuri , Georges G. E. Gielen Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaochun Duan , Kartikeya Mayaram A new approach for ring oscillator simulation using the harmonic balance method. [Citation Graph (0, 0)][DBLP ] Conf ] Zhengyong Zhu , Khosro Rouz , Manjit Borah , Chung-Kuan Cheng , Ernest S. Kuh Efficient transient simulation for transistor-level analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Bang Liu , Xuan Zeng , Yangfeng Su , Jun Tao , Zhaojun Bai , Charles Chiang , Dian Zhou Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Lizheng Zhang , Yuhen Hu , Charlie Chung-Ping Chen Block based statistical timing analysis with extended canonical timing model. [Citation Graph (0, 0)][DBLP ] Conf ] Lin Yuan , Gang Qu , Tiziano Villa , Alberto L. Sangiovanni-Vincentelli FSM re-engineering and its application in low power state encoding. [Citation Graph (0, 0)][DBLP ] Conf ] Aiqun Cao , Ruibing Lu , Cheng-Kok Koh Post-layout logic duplication for synthesis of domino circuits with complex gates. [Citation Graph (0, 0)][DBLP ] Conf ] Jin S. Zhang , Malgorzata Chrzanowska-Jeske , Alan Mishchenko , Jerry R. Burch Detecting support-reducing bound sets using two-cofactor symmetries. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek V. Shende , Stephen S. Bullock , Igor L. Markov Synthesis of quantum logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Plaza , Valeria Bertacco STACCATO: disjoint support decompositions from BDDs through symbolic kernels. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Schliebusch , Anupam Chattopadhyay , David Kammler , Gerd Ascheid , Rainer Leupers , Heinrich Meyr , Tim Kogel A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. [Citation Graph (0, 0)][DBLP ] Conf ] Naoki Tomono , Shunitsu Kohara , Jumpei Uchida , Yuichiro Miyaoka , Nozomu Togawa , Masao Yanagisawa , Tatsuo Ohtsuki A processor core synthesis system in IP-based SoC design. [Citation Graph (0, 0)][DBLP ] Conf ] Koushik Niyogi , Diana Marculescu Speed and voltage selection for GALS systems based on voltage/frequency islands. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Haubelt , Stephan Otto , Cornelia Grabbe , Jürgen Teich A system-level approach to hardware reconfigurable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Zili Shao , Qingfeng Zhuge , Chun Xue , Bin Xiao , Edwin Hsing-Mean Sha High-level synthesis for DSP applications using heterogeneous functional units. [Citation Graph (0, 0)][DBLP ] Conf ] Yasuo Sato , Shuji Hamada , Toshiyuki Maeda , Atsuo Takatori , Seiji Kajihara Evaluation of the statistical delay quality model. [Citation Graph (0, 0)][DBLP ] Conf ] Wenjing Rao , Alex Orailoglu , Ramesh Karri Fault tolerant nanoelectronic processor architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Shireesh Verma , Kiran Ramineni , Ian G. Harris An efficient control-oriented coverage metric. [Citation Graph (0, 0)][DBLP ] Conf ] Tai-Ying Jiang , Chien-Nan Jimmy Liu , Jing-Yang Jou An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Yang , Avi Puder Tightly integrate dynamic verification with formal verification: a GSTE based approach. [Citation Graph (0, 0)][DBLP ] Conf ] Satoshi Ono , Patrick H. Madden On structure and suboptimality in placement. [Citation Graph (0, 0)][DBLP ] Conf ] Pradeep Ramachandaran , Ameya R. Agnihotri , Satoshi Ono , Purushothaman Damodaran , Krishnaswami Srihari , Patrick H. Madden Optimal placement by branch-and-price. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Andrew B. Kahng , Chul-Hong Park Detailed placement for improved depth of focus and CD control. [Citation Graph (0, 0)][DBLP ] Conf ] Chen Li 0004 , Cheng-Kok Koh , Patrick H. Madden Floorplan management: incremental placement for gate sizing and buffer insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Ping You , Chun-Yen Tseng , Yu-Hui Huang , Po-Chiun Huang , TingTing Hwang , Sheng-Yu Hsu Low-power techniques for network security processors. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Pin Su , Chia-Lung Horng , Chih-Tsun Huang , Cheng-Wen Wu A configurable AES processor for enhanced security. [Citation Graph (0, 0)][DBLP ] Conf ] Yen-Fong Lee , Shi-Yu Huang , Sheng-Yu Hsu , I-Ling Chen , Cheng-Tao Shieh , Jian-Cheng Lin , Shih-Chieh Chang Power estimation starategies for a low-power security processor. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Pin Su , Chen-Hsing Wang , Kuo-Liang Cheng , Chih-Tsun Huang , Cheng-Wen Wu Design and test of a scalable security processor. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Chia Lin , Chung-Wen Huang , Jenq Kuen Lee System-level design space exploration for security processor prototyping in analytical approaches. [Citation Graph (0, 0)][DBLP ] Conf ] Hsinwei Chou , Yu-Hao Wang , Charlie Chung-Ping Chen Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Zhaojun Wo , Israel Koren Effective analytical delay model for transistor sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Kanak Agarwal , Dennis Sylvester , David Blaauw , Anirudh Devgan Achieving continuous VT performance in a dual VT process. [Citation Graph (0, 0)][DBLP ] Conf ] Dongwoo Lee , David Blaauw , Dennis Sylvester Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Cheng , Liang Deng , Martin D. F. Wong Floorplanning for 3-D VLSI design. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoping Tang , Ruiqi Tian , Martin D. F. Wong Optimal redistribution of white space for wire length minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Yongseok Cheon , Martin D. F. Wong Crowdedness-balanced multilevel partitioning for uniform resource utilization. [Citation Graph (0, 0)][DBLP ] Conf ] Ramprasad Ravichandran , Mike Niemier , Sung Kyu Lim Partitioning and placement for buildable QCA circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chanseok Hwang , Massoud Pedram PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits. [Citation Graph (0, 0)][DBLP ] Conf ] Jinbo Huang MUP: a minimal unsatisfiability prover. [Citation Graph (0, 0)][DBLP ] Conf ] Domagoj Babic , Alan J. Hu Integration of supercubing and learning in a SAT solver. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi A. Aloul , Arathi Ramani , Igor L. Markov , Karem A. Sakallah Dynamic symmetry-breaking for improved Boolean optimization. [Citation Graph (0, 0)][DBLP ] Conf ] ShengYu Shen , Ying Qin , Sikun Li A fast counterexample minimization approach with refutation analysis and incremental SAT. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Huang , Pushan Tang , Min Ding Sequential equivalence checking using cuts. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaolue Lai , Yayun Wan , Jaijeet S. Roychowdhury Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise. [Citation Graph (0, 0)][DBLP ] Conf ] Fang Liu , Sule Ozev Hierarchical analysis of process variation for mixed-signal systems. [Citation Graph (0, 0)][DBLP ] Conf ] Xuan Zeng , Bank Liu , Jun Tao , Charles Chiang , Dian Zhou A novel wavelet method for noise analysis of nonlinear circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mengmeng Ding , Glenn Wolfe , Ranga Vemuri An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Du , Wayne Dai Partial reluctance based circuit simulation is efficient and stable. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Srinivasan , Karam S. Chatha SAGA: synthesis technique for guaranteed throughput NoC architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Sudeep Pasricha , Nikil Dutt , Mohamed Ben-Romdhane Automated throughput-driven synthesis of bus-based communication architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Jae-Gon Lee , Wooseung Yang , Young-Su Kwon , Young-Il Kim , Chong-Min Kyung Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Mridul Agarwal , Kanak Agarwal , Dennis Sylvester , David Blaauw Statistical modeling of cross-coupling effects in VLSI interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Hong Li , Venkataramanan Balakrishnan , Cheng-Kok Koh , Guoan Zhong Compact and stable modeling of partial inductance and reluctance matrices. [Citation Graph (0, 0)][DBLP ] Conf ] Rami Beidas , Jianwen Zhu Scalable interprocedural register allocation for high level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Azadeh Davoodi , Ankur Srivastava Simultaneous floorplanning and resource binding: a probabilistic approach. [Citation Graph (0, 0)][DBLP ] Conf ] Anup Hosangadi , Farzan Fallah , Ryan Kastner Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions. [Citation Graph (0, 0)][DBLP ] Conf ] René Krenz , Elena Dubrova A fast algorithm for finding common multiple-vertex dominators in circuit graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Abdulkadir Utku Diril , Yuvraj Singh Dhillon , Abhijit Chatterjee , Adit D. Singh Low-power domino circuits using NMOS pull-up on off-critical paths. [Citation Graph (0, 0)][DBLP ] Conf ] Shengqi Yang , Wayne Wolf , Wenping Wang , Narayanan Vijaykrishnan , Yuan Xie Low-leakage robust SRAM cell design for sub-100nm technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Ismail Kadayif , Mahmut T. Kandemir , Guilin Chen Studying interactions between prefetching and cache line turnoff. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Han , Ahmet T. Erdogan , Tughrul Arslan , M. Hasan The development of high performance FFT IP cores through hybrid low power algorithmic methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Newton Cheung , Sri Parameswaran , Jörg Henkel Battery-aware instruction generation for embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Masanori Muroyama , Kosuke Tarumi , Koji Makiyama , Hiroto Yasuura A variation-aware low-power coding methodology for tightly coupled buses. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Wang , Jeremy R. Levitt Automatic assume guarantee analysis for assertion-based formal verification. [Citation Graph (0, 0)][DBLP ] Conf ] Pejman Lotfi-Kamran , Mohammad Hosseinabady , Hamid Shojaei , Mehran Massoumi , Zainalabedin Navabi TED+: a data structure for microprocessor verification. [Citation Graph (0, 0)][DBLP ] Conf ] René Krenz , Elena Dubrova Improved Boolean function hashing based on multiple-vertex dominators. [Citation Graph (0, 0)][DBLP ] Conf ] Rüdiger Ebendt , Rolf Drechsler Lower bounds for dynamic BDD reordering. [Citation Graph (0, 0)][DBLP ] Conf ] Xiushan Feng , Alan J. Hu , Jin Yang Partitioned model checking from software specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Yongqiang Lu , Cliff C. N. Sze , Xianlong Hong , Qiang Zhou , Yici Cai , Liang Huang , Jiang Hu Register placement for low power clock network. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Venkataraman , Cliff C. N. Sze , Jiang Hu Skew scheduling and clock routing for improved tolerance to process variations. [Citation Graph (0, 0)][DBLP ] Conf ] Vinil Varghese , Tom Chen , Peter Young Stability analysis of active clock deskewing systems using a control theoretic approach. [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Ching Douglas Lam , Cheng-Kok Koh Process variation robust clock tree routing. [Citation Graph (0, 0)][DBLP ] Conf ] Nacer-Eddine Zergainoh , Katalin Popovici , Ahmed Amine Jerraya , Pascal Urard IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kazutoshi Kobayashi , Masao Aramoto , Yoichi Yuyama , Akihiko Higuchi , Hidetoshi Onodera A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. [Citation Graph (0, 0)][DBLP ] Conf ] Lingfeng Li , Satoshi Goto , Takeshi Ikenaga An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. [Citation Graph (0, 0)][DBLP ] Conf ] Yanjun Zhang , Hu He , Yihe Sun A new register file access architecture for software pipelining in VLIW processors. [Citation Graph (0, 0)][DBLP ] Conf ] Minho Kim , Ingu Hwang , Soo-Ik Chae A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264. [Citation Graph (0, 0)][DBLP ] Conf ] Ying Yi , Mark Milward , Sami Khawam , Ioannis Nousias , Tughrul Arslan Automatic synthesis and scheduling of multirate DSP algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenyu Liu , Tughrul Arslan , Sami Khawam , Iain Lindsay A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines. [Citation Graph (0, 0)][DBLP ] Conf ] Yan Lin , Fei Li , Lei He Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarshee P. Bharadwaj , Rajan Konar , Poras T. Balsara , Dinesh Bhatia Exploiting temporal idleness to reduce leakage power in programmable architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Degalahal , Tim Tuan Methodology for high level estimation of FPGA power consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Suresh Srinivasan , Aman Gayasen , Narayanan Vijaykrishnan , Tim Tuan Leakage control in FPGA routing fabric. [Citation Graph (0, 0)][DBLP ] Conf ] K. Praveen Jayakar Thomas , Ram Singh Rana , Yong Lian A 1GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversion. [Citation Graph (0, 0)][DBLP ] Conf ] Min Chu , David J. Allstot An elitist distributed particle swarm algorithm for RF IC optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Min Chu , David J. Allstot Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Miao Li , Tad A. Kwasniewski , Shoujun Wang , Yuming Tao A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] Kenichi Okada , Yoshiaki Yoshihara , Hirotaka Sugawara , Kazuya Masu A dynamic reconfigurable RF circuit architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Zhangwen Tang , Jie He , Hongyan Jian , Haiqing Zhang , Jie Zhang , Hao Min Prediction of LC-VCOs' tuning curves with period calculation technique. [Citation Graph (0, 0)][DBLP ] Conf ] Zhihui Xiong , Jihua Chen , Sikun Li Hardware/software partitioning for platform-based design method. [Citation Graph (0, 0)][DBLP ] Conf ] Ernesto Wandeler , Lothar Thiele Abstracting functionality for modular performance analysis of hard real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dongkun Shin , Jihong Kim Optimizing intra-task voltage scheduling using data flow analysis. [Citation Graph (0, 0)][DBLP ] Conf ] John Conner , Yuan Xie , Mahmut T. Kandemir , Robert Dick , Greg M. Link FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection. [Citation Graph (0, 0)][DBLP ] Conf ] G. Chen , Mahmut T. Kandemir , Mary Jane Irwin , Gokhan Memik Compiler-directed selective data protection against soft errors. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant Saxena , Kumar N. Lalgudi , Hans J. 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