Journals in DBLP

Microprocessors and Microsystems
2005, volume: 29, number: 2-3

1. Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido
   Advances in FPGA tools and techniques. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:47-49 [Journal]
   
2. Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler
   Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:51-62 [Journal]
   
3. Rolf Enzler, Christian Plessl, Marco Platzner
   System-level performance evaluation of reconfigurable processors. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:63-73 [Journal]
   
4. M. A. Aguirre, Jonathan Noel Tombs, Vicente Baena Lecuyer, J. L. Mora, J. M. Carrasco, Antonio B. Torralba, Leopoldo García Franquelo
   Microprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systems. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:75-85 [Journal]
   
5. John A. Nestor
   L3: An FPGA-based multilayer maze routing accelerator. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:87-97 [Journal]
   
6. L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti
   Pseudo-online testing methodologies for various components of field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:99-119 [Journal]
   
7. Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Peter F. Curran, Kuan Zhou, Bryan S. Goda, John F. McDonald
   A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:121-131 [Journal]