Search the dblp DataBase

Publications of Author

1. Pedro C. Diniz, Joonseok Park
   Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines. [Citation Graph (0, 0)][DBLP]
   FCCM, 2000, pp:91-100 [Conf]
   
2. Pedro C. Diniz, Joonseok Park
   Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures. [Citation Graph (0, 0)][DBLP]
   FCCM, 2003, pp:207-217 [Conf]
   
3. Joonseok Park, Pedro C. Diniz
   Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines. [Citation Graph (0, 0)][DBLP]
   FCCM, 2003, pp:297-299 [Conf]
   
4. K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz
   Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations. [Citation Graph (0, 0)][DBLP]
   FCCM, 2003, pp:296- [Conf]
   
5. Pedro C. Diniz, Joonseok Park
   Data reorganization engines for the next generation of system-on-a-chip FPGAs. [Citation Graph (0, 0)][DBLP]
   FPGA, 2002, pp:237-244 [Conf]
   
6. Pedro C. Diniz, Joonseok Park
   Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures. [Citation Graph (0, 0)][DBLP]
   FPGA, 2003, pp:242- [Conf]
   
7. Pablo Moisset, Pedro C. Diniz, Joonseok Park
   Matching and searching analysis for parallel hardware implementation on FPGAs. [Citation Graph (0, 0)][DBLP]
   FPGA, 2001, pp:125-133 [Conf]
   
8. Nastaran Baradaran, Joonseok Park, Pedro C. Diniz
   Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:1113-1115 [Conf]
   
9. K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz
   Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:313-323 [Conf]
   
10. Joonseok Park, Pedro C. Diniz
    Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:221-226 [Conf]
    
11. Nastaran Baradaran, Pedro C. Diniz, Joonseok Park
    Extending the Applicability of Scalar Replacement to Multiple Induction Variables. [Citation Graph (0, 0)][DBLP]
    LCPC, 2004, pp:455-469 [Conf]
    
12. Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler
    Bridging the Gap between Compilation and Synthesis in the DEFACTO System. [Citation Graph (0, 0)][DBLP]
    LCPC, 2001, pp:52-70 [Conf]
    
13. Joonseok Park, Pedro C. Diniz, K. R. Shesha Shayee
    Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1420-1435 [Journal]
    
14. Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoungro So, Heidi E. Ziegler
    Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:51-62 [Journal]
    
15. Joonseok Park, Pedro C. Diniz
    Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:97-109 [Conf]
    
16. 
    An approach to developing reusable domain services for service oriented applications. [Citation Graph (, )][DBLP]
    
    
17. 
    CASS: A Context-Aware Simulation System for Smart Home. [Citation Graph (, )][DBLP]
    
    
18. 
    Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm. [Citation Graph (, )][DBLP]
    
    
19. 
    An approach to enhancing reusabilities in service development. [Citation Graph (, )][DBLP]