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Publications of Author

1. Nicola Bombieri, Franco Fummi, Davide Quaglia
   TLM/network design space exploration for networked embedded systems. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2006, pp:58-63 [Conf]
   
2. Nicola Bombieri, Franco Fummi, Graziano Pravadelli
   On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:1007-1012 [Conf]
   
3. Nicola Bombieri, Franco Fummi, Graziano Pravadelli
   At-Speed Functional Verification of Programmable Devices. [Citation Graph (0, 0)][DBLP]
   DFT, 2004, pp:386-394 [Conf]
   
4. Nicola Bombieri, Franco Fummi, Graziano Pravadelli
   Functional Verification of Networked Embedded Systems. [Citation Graph (0, 0)][DBLP]
   ISQED, 2005, pp:321-326 [Conf]
   
5. Nicola Bombieri, Andrea Fedeli, Franco Fummi
   Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2005, pp:239-240 [Conf]
   
6. Nicola Bombieri, Andrea Fedeli, Franco Fummi
   On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling. [Citation Graph (0, 0)][DBLP]
   MTV, 2005, pp:127-132 [Conf]
   
7. Nicola Bombieri, Franco Fummi, Graziano Pravadelli
   Incremental ABV for functional validation of TL-to-RTL design refinement. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:882-887 [Conf]
   
8. Nicola Bombieri, Franco Fummi, Graziano Pravadelli
   A methodology for abstracting RTL designs into TL descriptions. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2006, pp:103-112 [Conf]
   
9. Nicola Bombieri, Franco Fummi, Graziano Pravadelli, João Marques-Silva
   Towards Equivalence Checking Between TLM and RTL Models. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2007, pp:113-122 [Conf]
   
10. Nicola Bombieri, Franco Fummi, Graziano Pravadelli
    Hardware Design and Simulation for Verification. [Citation Graph (0, 0)][DBLP]
    SFM, 2006, pp:1-29 [Conf]
    
11. 
    Automatic customization of device drivers for IP-cores used with assorted CPU organizations. [Citation Graph (, )][DBLP]
    
    
12. 
    Abstraction of RTL IPs into embedded software. [Citation Graph (, )][DBLP]
    
    
13. 
    Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation. [Citation Graph (, )][DBLP]
    
    
14. 
    A Mutation Model for the SystemC TLM 2.0 Communication Interfaces. [Citation Graph (, )][DBLP]
    
    
15. 
    Correct-by-construction generation of device drivers based on RTL testbenches. [Citation Graph (, )][DBLP]
    
    
16. 
    Functional qualification of TLM verification. [Citation Graph (, )][DBLP]
    
    
17. 
    Hybrid, Incremental Assertion-Based Verification for TLM Design Flows. [Citation Graph (, )][DBLP]