Conferences in DBLP

International Conference on Formal Methods and Models for Co-Design (memocode)
2006 (conf/memocode/2006)

1. Rajeev Alur
   Games for formal design and verification of reactive systems. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2006, pp:3- [Conf]
   
2. Tevfik Bultan, Constance L. Heitmeyer
   Analyzing tabular requirements specifications using infinite state model checking. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2006, pp:7-16 [Conf]
   
3. Zijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivancic
   Mixed symbolic representations for model checking software programs. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2006, pp:17-26 [Conf]
   
4. Fei Xie, Guowu Yang, Xiaoyu Song
   Component-based hardware/software co-verification. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2006, pp:27-36 [Conf]
   
5. Hiren D. Patel, Sandeep K. Shukla, E. Mednick, Rishiyur S. Nikhil
   A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2006, pp:39-48 [Conf]
   
6. G. Singh, Sandeep K. Shukla
   Low-power hardware synthesis from TRS-based specifications. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2006, pp:49-58 [Conf]
   
7. Nirav Dave, Michael Pellauer, S. Gerding, Arvind
   802.11a transmitter: a case study in microarchitectural exploration. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2006, pp:59-68 [Conf]
   
8. Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu
   Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2006, pp:71-80 [Conf]
   
9. Alistair A. McEwan, S. Schneider
   A verified development of hardware using CSP/spl par/B. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2006, pp:81- [Conf]
   
10. M. Hsiao, S. Shukla, M. Gokhale, A. Lebeck
    Panel: Nano-computing - do we need new formal approaches? [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:85-86 [Conf]
    
11. Alexander Aiken
    Scalable program analysis using Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:89- [Conf]
    
12. Wolfgang Ecker, Volkan Esen, Michael Hull
    Execution semantics and formalisms for multi-abstraction TLM assertions. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:93-102 [Conf]
    
13. Nicola Bombieri, Franco Fummi, Graziano Pravadelli
    A methodology for abstracting RTL designs into TL descriptions. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:103-112 [Conf]
    
14. Niloofar Razavi, Marjan Sirjani
    Using Reo for formal specification and verification of system designs. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:113-122 [Conf]
    
15. R. Gupta
    Programming models and languages for SoC-implemented architectures. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:125- [Conf]
    
16. Myla Archer, Hongping Lim, Nancy A. Lynch, Sayan Mitra, Shinya Umeno
    Specifying and proving properties of timed I/O automata in the TIOA toolkit. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:129-138 [Conf]
    
17. E. Czeck, Ravi Nanavati, Joseph E. Stoy
    Reliable design with multiple clock domains. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:139-148 [Conf]
    
18. Flavius Gruian, Partha S. Roop, Zoran A. Salcic, Ivan Radojevic
    The SystemJ approach to system-level design. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:149-158 [Conf]
    
19. C. Seger
    Integrating design and verification - from simple idea to practical system. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:161- [Conf]
    
20. Klaus Schneider, Jens Brandt, Eric Vecchié
    Efficient code generation from synchronous programs. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:165-174 [Conf]
    
21. Julien Boucaron, Robert de Simone, Jean-Vivien Millo
    Latency-insensitive design and central repetitive scheduling. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:175-183 [Conf]
    
22. Bart D. Theelen, Marc Geilen, Twan Basten, Jeroen Voeten, Stefan Valentin Gheorghita, Sander Stuijk
    A scenario-aware data flow model for combined long-run average and worst-case performance analysis. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:185-194 [Conf]
    
23. Masahiro Fujita, Subash Shankar, S. Shunsuke
    Equivalence checking: a rule-based approach. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:197- [Conf]
    
24. Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
    Formal methods for checking realizability of coalitions in 3-party systems. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:198- [Conf]
    
25. Qi Zhu, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli
    A semantic-driven synthesis flow for platform-based design. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:199- [Conf]
    
26. Iñigo Ugarte, Pablo Sanchez
    Assertion checking of control dominated systems with nonlinear solvers. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:200- [Conf]
    
27. Frederic Doucet, Ingolf Krüger, Rajesh K. Gupta, R. K. Shyamasundar
    Compositional interaction specifications for SystemC. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:201- [Conf]
    
28. Olivier Tardieu, Stephen A. Edwards
    R-SHIM: deterministic concurrency with recursion and shared variables. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:202- [Conf]