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Chandu Visweswariah: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hongliang Chang, Vladimir Zolotov, Sambasivan Narayan, Chandu Visweswariah
    Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:71-76 [Conf]
  2. Chandu Visweswariah
    Death, taxes and failing chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:343-347 [Conf]
  3. Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah
    Criticality computation in parameterized statistical timing. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:63-68 [Conf]
  4. Jurjen Westra, Dirk-Jan Jongeneel, Ralph H. J. M. Otten, Chandu Visweswariah
    Time Budgeting in a Wireplanning Context. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10436-10441 [Conf]
  5. Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov
    Gate sizing using incremental parameterized statistical timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:1029-1036 [Conf]
  6. Chandu Visweswariah
    Statistical analysis and design: from picoseconds to probabilities. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:2- [Conf]
  7. Chandu Visweswariah
    Statistical analysis and optimization in the presence of gate and interconnect delay variations. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:37- [Conf]
  8. Chandu Visweswariah
    Fear, uncertainty and statistics. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:169- [Conf]

  9. Static timing: Back to our roots. [Citation Graph (, )][DBLP]


  10. A moment-based effective characterization waveform for static timing analysis. [Citation Graph (, )][DBLP]


  11. Statistical ordering of correlated timing quantities and its application for path ranking. [Citation Graph (, )][DBLP]


  12. Statistical multilayer process space coverage for at-speed test. [Citation Graph (, )][DBLP]


  13. Transistor sizing of custom high-performance digital circuits with parametric yield considerations. [Citation Graph (, )][DBLP]


  14. Incremental Criticality and Yield Gradients. [Citation Graph (, )][DBLP]


  15. Optimal Margin Computation for At-Speed Test. [Citation Graph (, )][DBLP]


  16. Variation-aware performance verification using at-speed structural test and statistical timing. [Citation Graph (, )][DBLP]


  17. Compact modeling of variational waveforms. [Citation Graph (, )][DBLP]


  18. Statistical path selection for at-speed test. [Citation Graph (, )][DBLP]


  19. Voltage binning under process variation. [Citation Graph (, )][DBLP]


  20. Pre-ATPG path selection for near optimal post-ATPG process space coverage. [Citation Graph (, )][DBLP]


  21. Plenary Speech 2P2: Statistical Techniques to Achieve Robustness and Quality. [Citation Graph (, )][DBLP]


  22. A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). [Citation Graph (, )][DBLP]


  23. Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power. [Citation Graph (, )][DBLP]


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