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Matthew R. Guthaus: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown
    Process-induced skew reduction in nominal zero-skew clock trees. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:84-89 [Conf]
  2. Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown
    Increasing the number of effective registers in a low-power processor using a windowed register file. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:125-136 [Conf]
  3. Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown
    Clock buffer and wire sizing using sequential programming. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1041-1046 [Conf]
  4. Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Matthew R. Guthaus, Richard B. Brown
    A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:520-525 [Conf]
  5. Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown
    Optimization objectives and models of variation for statistical gate sizing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:313-316 [Conf]
  6. Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov
    Gate sizing using incremental parameterized statistical timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:1029-1036 [Conf]
  7. Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown
    Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:8, pp:998-1012 [Journal]

  8. Clock tree synthesis with data-path sensitivity matching. [Citation Graph (, )][DBLP]


  9. Non-uniform clock mesh optimization with linear programming buffer insertion. [Citation Graph (, )][DBLP]


  10. Measuring and modeling variabilityusing low-cost FPGAs. [Citation Graph (, )][DBLP]


  11. Analysis of power supply induced jitter in actively de-skewed multi-core systems. [Citation Graph (, )][DBLP]


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