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Publications of Author

1. Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
   FPGA technology mapping: a study of optimality. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:427-432 [Conf]
   
2. Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
   Incremental retiming for FPGA physical synthesis. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:433-438 [Conf]
   
3. Deshanand P. Singh, Stephen Dean Brown
   The case for registered routing switches in field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
   FPGA, 2001, pp:161-169 [Conf]
   
4. Deshanand P. Singh, Stephen Dean Brown
   Integrated retiming and placement for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
   FPGA, 2002, pp:67-76 [Conf]
   
5. Deshanand P. Singh, Stephen Dean Brown
   Constrained clock shifting for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
   FPGA, 2002, pp:121-126 [Conf]
   
6. Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
   FPGA PLB Evaluation using Quantified Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:19-24 [Conf]
   
7. Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown
   Post-Placement BDD-Based Decomposition for FPGAs. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:31-38 [Conf]
   
8. Deshanand P. Singh, Stephen Dean Brown
   Incremental placement for layout driven optimizations on FPGAs. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2002, pp:752-759 [Conf]
   
9. Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
   Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:135-142 [Conf]
   
10. Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
    FPGA Logic Synthesis Using Quantified Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    SAT, 2005, pp:444-450 [Conf]
    
11. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
    Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:3-8 [Conf]
    
12. Deshanand P. Singh, Stephen Dean Brown
    An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:41-50 [Conf]
    
13. Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown
    Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:28-33 [Conf]
    
14. Deshanand P. Singh, Stephen Dean Brown
    An area-efficient timing closure technique for FPGAs using Shannon's expansion. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:167-173 [Journal]
    
15. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
    Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:895-903 [Journal]
    
16. 
    Incremental placement for structured ASICs using the transportation problem. [Citation Graph (, )][DBLP]