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Journals in DBLP

Integration
2007, volume: 40, number: 2

  1. Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Niamat, Dimitrios Soudris, Srinivasa Vemuru
    Preface. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:61- [Journal]
  2. Kyung Tae Do, Young hwan Kim, Haeng Seon Son
    Timing modeling of latch-controlled sub-systems. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:62-73 [Journal]
  3. Konstantinos Tatas, G. Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis
    Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:74-93 [Journal]
  4. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
    Constrained algorithmic IP design for system-on-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:94-105 [Journal]
  5. Bill Lin
    Compiling concurrent programs for embedded sequential execution. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:106-117 [Journal]
  6. Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi
    A new array architecture for signed multiplication using Gray encoded radix-2m operands. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:118-132 [Journal]
  7. Martin John Burbidge, Jim Tijou
    Towards generic charge-pump phase-locked loop, jitter estimation techniques using indirect on chip methods. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:133-148 [Journal]
  8. Zahra Sadat Ebadi, Alireza Nasiri Avanaki, Resve Saleh, André Ivanov
    Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:149-160 [Journal]
  9. Hung-Mu Chou, Jam-Wen Lee, Yiming Li
    A floating gate design for electrostatic discharge protection circuits. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:161-166 [Journal]
  10. Deshanand P. Singh, Stephen Dean Brown
    An area-efficient timing closure technique for FPGAs using Shannon's expansion. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:167-173 [Journal]
  11. Ling Wang, Yingtao Jiang, Henry Selvaraj
    Scheduling and optimal voltage selection with multiple supply voltages under resource constraints. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:174-182 [Journal]
  12. Sankalp Kallakuri, Alex Doboli, Simona Doboli
    Applying stochastic modeling to bus arbitration for systems-on-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:183-191 [Journal]
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