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Fabio Campi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andrea Cappelli, Andrea Lodi, Claudio Mucci, Mario Toma, Fabio Campi
    A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:332-333 [Conf]
  2. Andrea Lodi, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Mario Toma, Fabio Campi
    Routing architecture for multi-context FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:246- [Conf]
  3. Andrea Lodi, Mario Toma, Fabio Campi
    A pipelined configurable gate array for embedded processors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:21-30 [Conf]
  4. Andrea Lodi, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Fabio Campi, Mario Toma
    Compact Buffered Routing Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:179-188 [Conf]
  5. Fabio Campi, Andrea Cappelli, Roberto Guerrieri, Andrea Lodi, Mario Toma, Alberto La Rosa, Luciano Lavagno, Claudio Passerone, Roberto Canegallo
    A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:171- [Conf]
  6. Claudio Mucci, Fabio Campi, Antonio Deledda, Alberto Fazzi, Mirco Ferri, Massimo Bocchi
    A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  7. Andrea Lodi, Carlo Chiesa, Fabio Campi, Mario Toma
    A flexible LUT-based carry chain for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:133-136 [Conf]
  8. Andrea Lodi, Luca Ciccarelli, Andrea Cappelli, Fabio Campi, Mario Toma
    Decoder-Based Multi-Context Interconnect Architecture. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:231-233 [Conf]
  9. Aldo Romani, Fabio Campi, S. Ronconi, Marco Tartagni, Gianni Medoro, Nicolò Manaresi
    A System-on-a-Programmable-Chip for Real-Time Control of Massively Parallel Arrays of Biosensors and Actuators. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:236-241 [Conf]
  10. L. Bolcioni, Fabio Campi, Roberto Canegallo, Roberto Guerrieri
    A low-power system-on-chip for the documentation of road accidents. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:11, pp:1493-1501 [Journal]
  11. Claudio Mucci, Luca Vanzolini, Fabio Campi, Mario Toma
    Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:355-360 [Conf]
  12. Fabio Campi, Antonio Deledda, Matteo Pizzotti, Luca Ciccarelli, Pier Luigi Rolandi, Claudio Mucci, Andrea Lodi, Arseni Vitkovski, Luca Vanzolini
    A dynamically adaptive DSP for heterogeneous reconfigurable platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:9-14 [Conf]
  13. Fabio Campi, P. Zoffoli, Claudio Mucci, Massimo Bocchi, Antonio Deledda, M. De Dominicis, Arseni Vitkovski
    A stream register file unit for reconfigurable processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  14. Claudio Mucci, Massimo Bocchi, Mario Toma, Fabio Campi
    A case-study on multimedia applications for the XiRisc reconfigurable processor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  15. Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor. [Citation Graph (, )][DBLP]


  16. Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array. [Citation Graph (, )][DBLP]


  17. Reconfigurable hardware: The holy grail of matching performance with programming productivity. [Citation Graph (, )][DBLP]


  18. Sustainable (re-) configurable solutions for the high volume SoC market. [Citation Graph (, )][DBLP]


  19. An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC. [Citation Graph (, )][DBLP]


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