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Publications of Author

1. Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De
   A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. [Citation Graph (0, 0)][DBLP]
   ICCD, 2005, pp:567-573 [Conf]
   
2. Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak
   Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2006, pp:606-612 [Conf]
   
3. Maryam Ashouei, Muhammad M. Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril
   Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2007, pp:711-716 [Conf]
   
4. Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterj
   Design of Soft Error Resilient Linear Digital Filters Using Checksum-Based Probabilistic Error Correction. [Citation Graph (0, 0)][DBLP]
   VTS, 2006, pp:208-213 [Conf]
   
5. Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee
   Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors. [Citation Graph (0, 0)][DBLP]
   VTS, 2007, pp:125-130 [Conf]
   
6. Muhammad M. Nisar, Maryam Ashouei, Abhijit Chatterjee
   Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2007, pp:173-182 [Conf]
   
7. Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee
   Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study. [Citation Graph (0, 0)][DBLP]
   European Test Symposium, 2006, pp:35-42 [Conf]
   
8. 
   Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS. [Citation Graph (, )][DBLP]