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Chua-Chin Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chua-Chin Wang, Cheng-Fa Tsai
    A Novel Neural Architecture with High Storage Capacity. [Citation Graph (0, 0)][DBLP]
    IJCNN (5), 2000, pp:617-621 [Conf]
  2. Chua-Chin Wang, Ya-Hsin Hsueh, U. Fat Chio, Yu-Tzu Hsiao
    A C-less ASK demodulator for implantable neural interfacing chips. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:57-60 [Conf]
  3. Chua-Chin Wang, Ching-Li Lee, Li-Ping Lin, Yih-Long Tseng
    Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:356-359 [Conf]
  4. Chua-Chin Wang, Yih-Long Tseng, Tzung-Je Lee, Ron Hu
    High-PSR bias circuitry for NTSC sync separation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:329-332 [Conf]
  5. Chua-Chin Wang, Jeng-Ming Wu
    Analysis and Current-Mode Implementation of Asymptotically Stable Exponential Bidirectional Associative Memory. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:421-424 [Conf]
  6. Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang
    A 1.25 GHz 32-bit tree-structured carry lookahead adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:80-83 [Conf]
  7. Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen
    A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:528-531 [Conf]
  8. Chua-Chin Wang, Cheng-Fa Tsai
    Theoretical expectation value of the capacity of fuzzy polynomial bidirectional hetero-correlator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 1999, pp:583-586 [Conf]
  9. Chua-Chin Wang, Ya-Hsin Hsueh, Sen-Fu Hong, Rong-Sui Kao
    A phase-adjustable negative phase shifter using a single-shot locking method. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:933-936 [Conf]
  10. Chua-Chin Wang, Gang-Neng Sung
    A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:405-410 [Conf]
  11. Chua-Chin Wang, Gang-Neng Sung, Jia-Hao Li
    Codec Design for Variable-Length to Fixed-Length Data Conversion for H.263. [Citation Graph (0, 0)][DBLP]
    IIH-MSP, 2006, pp:483-486 [Conf]
  12. Chenn-Jung Huang, Wei Kuang Lai, Chua-Chin Wang, Yu-Jyr Jin, Hsin Wei Chen
    A ratioed channel assignment scheme for initial and handoff calls in mobile cellular systems. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2001, v:24, n:3-4, pp:308-318 [Journal]
  13. Chenn-Jung Huang, Chua-Chin Wang, Chi-Feng Wu
    Image Processing Techniques for Wafer Defect Cluster Identification. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:2, pp:44-48 [Journal]
  14. Chua-Chin Wang, Hon-Son Don
    A Polar Model for Evidential Reasoning. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1994, v:77, n:3-4, pp:195-226 [Journal]
  15. Chua-Chin Wang, Hon-Son Don
    A Modified Measure for Fuzzy Subsethood. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1994, v:79, n:3-4, pp:223-232 [Journal]
  16. Chua-Chin Wang, Hon-Son Don
    The Majority Theorem of Centralized Multiple BAMs Networks. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1998, v:110, n:3-4, pp:179-193 [Journal]
  17. Chua-Chin Wang, Cheng-Fa Tsai
    Fuzzy data processing using polynomial bidirectional hetero-associative network. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 2000, v:125, n:1-4, pp:167-179 [Journal]
  18. Chua-Chin Wang, Cheng-Fa Tsai, Yu-Tsun Chien
    Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2001, v:17, n:2, pp:313-324 [Journal]
  19. Chua-Chin Wang
    Practical Capacity and Attraction Radix Analysis of Exponential Bidirectional Associative Memory. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1996, v:12, n:4, pp:511-523 [Journal]
  20. Chua-Chin Wang, Chenn-Jung Huang, Shiou-Ming Hwang
    A deterministic capacity-finding method for multi-valued exponential BAM. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part A, 2000, v:30, n:6, pp:817-819 [Journal]
  21. Chua-Chin Wang, Chang-Rong Tsai
    Data compression by the recursive algorithm of exponential bidirectional associative memory. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part B, 1998, v:28, n:2, pp:125-134 [Journal]
  22. Chua-Chin Wang, Tzung-Je Lee, Yu-Tzu Hsiao, U. Fat Chio, Chi-Chun Huang, J.-J. J. Chin, Ya-Hsin Hsueh
    A multiparameter implantable microstimulator SOC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1399-1402 [Journal]
  23. Chua-Chin Wang, Yih-Long Tseng, Chih-Chiang Chiu
    A temperature-insensitive self-recharging circuitry used in DRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:405-408 [Journal]
  24. Chua-Chin Wang, Yih-Long Tseng, Hon-Yuan Leo, Ron Hu
    A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:901-909 [Journal]
  25. Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Ron Hu
    A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1377-1381 [Journal]
  26. Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Chih-Chen Li, Ron Hu
    A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:895-900 [Journal]
  27. Chua-Chin Wang, Chi-Chun Huang, Jian-Sing Liou, Yan-Jhin Ciou, I-Yu Huang, Chih-Peng Li, Yun-Chin Lee, Wen-Jen Wu
    An Implantable Long-term Bladder Urine Pressure Measurement System with a 1-atm Canceling Instrumentation Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2383-2386 [Conf]
  28. Chua-Chin Wang, Gang-Neng Sung, Kuan-Wen Fang, Sheng-Lun Tseng
    A Low-power Sensorless Inverter Controller of Brushless DC Motors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2435-2438 [Conf]
  29. Chua-Chin Wang, Ching-Li Lee, Wun-Ji Lin
    A 4-Kb low power 4-T SRAM design with negative word-line gate drive. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  30. Chua-Chin Wang, Jian-Ming Huang, Chih-Yi Chang, Kuang-Ting Cheng, Chih-Peng Li
    A 6.57 mW ZigBee transceiver for 868/915 MHz band. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  31. Chua-Chin Wang, Po-Ming Lee, Jun-Jie Wang, Chenn-Jung Huang
    Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:737-740 [Journal]
  32. Chua-Chin Wang, Ya-Hsin Hsueh, Ying-Pei Chen
    An area-saving decoder structure for ROMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:581-589 [Journal]

  33. A power-aware 2-dimensional bypassing multiplier using cell-based design flow. [Citation Graph (, )][DBLP]


  34. Power-saving nano-scale DRAMs with an adaptive refreshing clock generator. [Citation Graph (, )][DBLP]


  35. A mini-invasive multi-function bladder urine pressure measurement system. [Citation Graph (, )][DBLP]


  36. A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR. [Citation Graph (, )][DBLP]


  37. An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V Sensitivity. [Citation Graph (, )][DBLP]


  38. An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording. [Citation Graph (, )][DBLP]


  39. Engery-Efficient Double-Edge Triggered Flip-Flop Design. [Citation Graph (, )][DBLP]


  40. A Low-power 4-T SAM Design for OFDM Demodulators in DVB Receiversers. [Citation Graph (, )][DBLP]


  41. A 140-dB CMRR Low-noise Instrumentation Amplifier for Neural Signal Sensing. [Citation Graph (, )][DBLP]


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