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Publications of Author

1. Chi-Feng Wu, Cheng-Wen Wu
   Testing Interconnects of Dynamic Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1999, pp:279-282 [Conf]
   
2. Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
   Collaboration between Industry and Academia in Test Research. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2000, pp:17-0 [Conf]
   
3. Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang
   A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2001, pp:103-0 [Conf]
   
4. Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
   A built-in self-test and self-diagnosis scheme for embedded SRAM. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2000, pp:45-50 [Conf]
   
5. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
   Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. [Citation Graph (0, 0)][DBLP]
   DAC, 2001, pp:301-306 [Conf]
   
6. Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
   Flash Memory Built-In Self-Test Using March-Like Algorithm. [Citation Graph (0, 0)][DBLP]
   DELTA, 2002, pp:137-141 [Conf]
   
7. Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
   RAMSES: A Fast Memory Fault Simulator. [Citation Graph (0, 0)][DBLP]
   DFT, 1999, pp:165-173 [Conf]
   
8. Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
   Error Catch and Analysis for Semiconductor Memories Using March Tests. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2000, pp:468-471 [Conf]
   
9. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
   Simulation-Based Test Algorithm Generation for Random Access Memories. [Citation Graph (0, 0)][DBLP]
   VTS, 2000, pp:291-296 [Conf]
   
10. Chenn-Jung Huang, Chua-Chin Wang, Chi-Feng Wu
    Image Processing Techniques for Wafer Defect Cluster Identification. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:2, pp:44-48 [Journal]
    
11. Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang
    A Programmable BIST Core for Embedded DRAM. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:1, pp:59-70 [Journal]
    
12. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
    Fault simulation and test algorithm generation for random accessmemories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:480-490 [Journal]
    
13. Hsiao-Hwa Chen, Jin-Xiao Lin, Shin-Wei Chu, Chi-Feng Wu, Guo-Sheng Chen
    Isotropic air-interface technologies for fourth generation wireless communications. [Citation Graph (0, 0)][DBLP]
    Wireless Communications and Mobile Computing, 2003, v:3, n:6, pp:687-704 [Journal]
    
14. Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
    Built-in redundancy analysis for memory yield improvement. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:386-399 [Journal]
    
15. 
    Application of neural networks and genetic algorithms to the screening for high quality chips. [Citation Graph (, )][DBLP]