Search the dblp DataBase

Publications of Author

1. Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III
   A technique for high-speed, fine-resolution pattern generation and its CMOS implementation. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 1995, pp:131-149 [Conf]
   
2. Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
   Low-power design methodology for an on-chip bus with adaptive bandwidth capability. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:628-633 [Conf]
   
3. Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray
   Concurrent timing optimization of latch-based digital systems. [Citation Graph (0, 0)][DBLP]
   ICCD, 1995, pp:680-0 [Conf]
   
4. Wentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III
   Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions. [Citation Graph (0, 0)][DBLP]
   ISCA, 1988, pp:167-174 [Conf]
   
5. Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
   Accurate delay model and experimental verification for current/voltage mode on-chip interconnects. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:169-172 [Conf]
   
6. Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III
   High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1995, pp:405-408 [Conf]
   
7. C. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III
   Theoretical and Practical Issues in CMOS Wave Pipelining. [Citation Graph (0, 0)][DBLP]
   VLSI, 1991, pp:397-409 [Conf]
   
8. Robert M. Burger, Ralph K. Cavin III, William C. Holton, Larry W. Sumney
   The Impact of ICs on Computer Technology. [Citation Graph (0, 0)][DBLP]
   IEEE Computer, 1984, v:17, n:10, pp:88-95 [Journal]
   
9. Wentai Liu, Thomas H. Hildebrandt, Ralph K. Cavin III
   Hamiltonian Cycles in the Shuffle-Exchange Network. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1989, v:38, n:5, pp:745-750 [Journal]
   
10. C. Thomas Gray, Wentai Liu, Ralph K. Cavin III
    Timing constraints for wave-pipelined systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:987-1004 [Journal]
    
11. Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III
    Integrated parametric timing optimization of digital systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:482-489 [Journal]
    
12. Stephen K. Jones, Ralph K. Cavin III, William M. Reed
    Analysis of error-gradient adaptive linear estimators for a class of stationary dependent processes. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Information Theory, 1982, v:28, n:2, pp:318-329 [Journal]
    
13. Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards
    A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:876-880 [Journal]
    
14. Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
    Current-mode signaling in deep submicrometer global interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:406-417 [Journal]
    
15. 
    The Viability of Cellular Automata Architectures for General Purpose Computing. [Citation Graph (, )][DBLP]
    
    
16. 
    An Assessment of Integrated Digital Cellular Automata Architectures. [Citation Graph (, )][DBLP]
    
    
17. 
    Boolean Logic and Alternative Information-Processing Devices. [Citation Graph (, )][DBLP]
    
    
18. 
    Emerging Nanoscale Memory and Logic Devices: A Critical Assessment. [Citation Graph (, )][DBLP]
    
    
19. 
    Emerging Research Architectures. [Citation Graph (, )][DBLP]