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Masaaki Kondo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura
    Data Movement Optimization for Software-Controlled On-Chip Memory. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2004, pp:120-127 [Conf]
  2. Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura
    An intra-task dvfs technique based on statistical analysis of hardware events. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:123-130 [Conf]
  3. Masaaki Kondo, Hiroshi Nakamura
    A Small, Fast and Low-Power Register File by Bit-Partitioning. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:40-49 [Conf]
  4. Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku
    SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:105-0 [Conf]
  5. Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku
    Software Controlled Reconfigurable On-Chip Memory for High Performance Computing. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:15-32 [Conf]
  6. Masaaki Kondo, Mitsugu Iwamoto, Hiroshi Nakamura
    Cache Line Impact on 3D PDE Solvers. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:301-309 [Conf]
  7. Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
    Energy-efficient dynamic instruction scheduling logic through instruction grouping. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:43-48 [Conf]
  8. Masaaki Kondo, Hiroshi Nakamura
    Dynamic Processor Throttling for Power Efficient Computations. [Citation Graph (0, 0)][DBLP]
    PACS, 2004, pp:120-134 [Conf]
  9. Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
    Dynamic Instruction Cascading on GALS Microprocessors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:30-39 [Conf]
  10. Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya
    Skewed Checkpointing for Tolerating Multi-Node Failures. [Citation Graph (0, 0)][DBLP]
    SRDS, 2004, pp:116-125 [Conf]
  11. Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, Mitsuhisa Sato
    SCIMA-SMP: on-chip memory processor architecture for SMP. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:121-128 [Conf]
  12. Masaaki Kondo, Motonobu Fujita, Hiroshi Nakamura
    Software-controlled on-chip memory for high-performance and low-power computing. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2002, v:30, n:3, pp:7-8 [Journal]
  13. Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
    Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:797-802 [Conf]
  14. Masaaki Kondo, Yoshimichi Ikeda, Hiroshi Nakamura
    A High Performance Cluster System Design by Adaptie Power Control. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]

  15. Power reduction of chip multi-processors using shared resource control cooperating with DVFS. [Citation Graph (, )][DBLP]


  16. A fine-grain dynamic sleep control scheme in MIPS R3000. [Citation Graph (, )][DBLP]


  17. Cooperative shared resource access control for low-power chip multiprocessors. [Citation Graph (, )][DBLP]


  18. Adaptive power gating for function units in a microprocessor. [Citation Graph (, )][DBLP]


  19. Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. [Citation Graph (, )][DBLP]


  20. Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. [Citation Graph (, )][DBLP]


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