Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
1992, volume: 11, number: 4

1. Stefaan Note, Francky Catthoor, Gert Goossens, Hugo De Man
   Combined hardware selection and pipelining in high-performance data-path design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:413-423 [Journal]
   
2. Thomas F. Hayes, John J. Barrett
   Modeling of multiconductor systems for packaging and interconnecting high-speed digital IC's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:424-431 [Journal]
   
3. Eugene Z. Xia, Resve A. Saleh
   Parallel waveform-Newton algorithms for circuit simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:432-442 [Journal]
   
4. Eduard Cerny, John P. Hayes, Nicholas C. Rumin
   Accuracy of magnitude-class calculations in switch-level modeling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:443-452 [Journal]
   
5. Allen C.-H. Wu, Daniel D. Gajski
   Partitioning algorithms for layout synthesis from register-transfer netlists. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:453-463 [Journal]
   
6. Nobuo Funabiki, Yoshiyasu Takefuji
   A parallel algorithm for channel routing problems [VLSI]. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:464-474 [Journal]
   
7. Chung-Kuan Cheng, Ximtie Deng, Yuh-Zen Liao, So-Zen Yao
   Symbolic layout compaction under conditional design rules. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:475-486 [Journal]
   
8. Walter B. Richardson, Graham F. Carey, Brian J. Mulvaney
   Modeling phosphorus diffusion in three dimensions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:487-496 [Journal]
   
9. Zeyi Wang, Qiming Wu
   A two-dimensional resistance simulator using the boundary element method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:497-504 [Journal]
   
10. Keith R. Green, Jerry G. Fossum
    A pragmatic approach to integrated process/device/circuit simulation for IC technology development. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:505-512 [Journal]
    
11. George L. Matthaei, Gilbert C. Chinn, Charles H. Plott, Nadir Dagli
    A simplified means for computation for interconnect distributed capacitances and inductances. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:513-524 [Journal]
    
12. Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao, Michael Nicolaidis
    An SFS Berger check prediction ALU and its application to self-checking processor designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:525-540 [Journal]