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Resve A. Saleh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yun-Cheng Ju, Resve A. Saleh
    Incremental Techniques for the Identification of Statically Sensitizable Critical Paths. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:541-546 [Conf]
  2. Yun-Cheng Ju, Resve A. Saleh
    Incremental Circuit Simulation Using Waveform Relaxation. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:8-11 [Conf]
  3. Gih-Guang Hung, Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh
    Parallel Circuit Simulation Using Hierarchical Relaxation. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:394-399 [Conf]
  4. Ken Kubiak, Steven Parkes, W. Kent Fuchs, Resve A. Saleh
    Exact Evaluation of Diagnostic Test Resolution. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:347-352 [Conf]
  5. Yun-Cheng Ju, Fred L. Yang, Resve A. Saleh
    Mixed-Mode Incremental Simulation and Concurrent Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:158-161 [Conf]
  6. Resve A. Saleh, David Overhauser, Sandy Taylor
    Full-chip verification of UDSM designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:453-460 [Conf]
  7. Jaidip Singh, Resve A. Saleh
    iMACSIM: A Program for Multi-Level Analog Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:16-19 [Conf]
  8. Yun-Cheng Ju, Resve A. Saleh
    Identification of Viable Paths Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:638-641 [Conf]
  9. Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh
    Parallel Event-Driven Waveform Relaxation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:101-104 [Conf]
  10. Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov
    Analog IP design flow for SoC applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:676-679 [Conf]
  11. S. Shang, Shahriar Mirabbasi, Resve A. Saleh
    A technique for DC-offset removal and carrier phase error compensation in integrated wireless receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:173-176 [Conf]
  12. Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh
    Improving Parallel Circuit Simulation Using High-Level Waveforms. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:728-731 [Conf]
  13. Xiongfei Meng, Resve A. Saleh, Karim Arabi
    Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:266-271 [Conf]
  14. Dipanjan Sengupta, Resve A. Saleh
    Power-Delay Metrics Revisited for 90nm CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:291-296 [Conf]
  15. Resve A. Saleh, G. Lim, T. Kadowaki, K. Uchiyama
    Trends in Low Power Digital System-on-Chip Designs (invited). [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:373-0 [Conf]
  16. Mohsen Nahvi, André Ivanov, Resve A. Saleh
    Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1176-1184 [Conf]
  17. Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli
    Design, Synthesis, and Test of Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:404-413 [Journal]
  18. Resve A. Saleh
    An approach that will NoC your SoCs off! [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:488- [Journal]
  19. Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh
    Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:8, pp:1025-1040 [Journal]
  20. Gih-Guang Hung, Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh
    Improving the performance of parallel relaxation-based circuit simulators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1762-1774 [Journal]
  21. Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh
    Consistency checking and optimization of macromodels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:957-967 [Journal]
  22. J. G. Mueller, Brian A. A. Antao, Resve A. Saleh
    A multifrequency technique for frequency response computation with application to switched-capacitor circuits with nonlinearities. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:7, pp:775-790 [Journal]
  23. Resve A. Saleh, Brian A. A. Antao, Jaidip Singh
    Multilevel and mixed-domain simulation of analog circuits and systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:68-82 [Journal]
  24. Resve A. Saleh, Syed Zakir Hussain, Steffen Rochel, David Overhauser
    Clock skew verification in the presence of IR-drop in the powerdistribution network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:6, pp:635-644 [Journal]
  25. Resve A. Saleh, A. Richard Newton
    The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1286-1298 [Journal]
  26. Resve A. Saleh, Jacob K. White
    Accelerating relaxation algorithms for circuit simulation using waveform-Newton and step-size refinement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:951-958 [Journal]
  27. Eugene Z. Xia, Resve A. Saleh
    Parallel waveform-Newton algorithms for circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:432-442 [Journal]
  28. Reza Molavi, Shahriar Mirabbasi, R. Saleh
    A high-speed low-energy dynamic PLA using an input-isolation scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  29. Application-driven floorplan-aware voltage island design. [Citation Graph (, )][DBLP]


  30. Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits. [Citation Graph (, )][DBLP]


  31. A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS. [Citation Graph (, )][DBLP]


  32. A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks. [Citation Graph (, )][DBLP]


  33. Active decap design considerations for optimal supply noise reduction. [Citation Graph (, )][DBLP]


  34. Supply voltage selection in Voltage Island based SoC design. [Citation Graph (, )][DBLP]


  35. Power Supply Noise in SoCs: Metrics, Management, and Measurement. [Citation Graph (, )][DBLP]


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